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Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA
are used as CS output pins, they go to the high-impedance state at the same time as RES
to PB
3
goes low. Clock pin P6
P6
/φ
7
RES
Internal reset
signal
A
to A
20
0
CS
0
AS, RD
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
I/O port,
PA
/A
to PA
/A
4
23
6
CS
to CS
7
1
Figure D.2 Reset during Memory Access (Modes 3 and 4)
Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external
memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS,
RD, HWR, and LWR go high, and the address bus and D
/φ goes to the output state at the next rise of φ after RES goes low.
Clock pin P6
7
go high, and D
0
to PA
are used as address bus pins, or when P8
4
6
/φ goes to the output state at the next rise of φ after RES goes low.
7
Access to external
memory
T1
,
21
to D
go to the high-impedance state.
15
0
T2
T3
to D
go to the high-impedance state.
15
0
to P8
and PB
3
1
H'00000
High impedance
High impedance
0
931
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