Serial Status Register (Ssr) - Hitachi H8/3062 Hardware Manual

13.2.2

Serial Status Register (SSR)

The function of SSR bit 4 is modified in smart card interface mode. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit 7
TDRE
Initial value 1
R/(W) *
Read/Write
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detect framing errors.
Bit 4
ERS Description
0 Indicates normal transmission, with no error signal returned
[Clearing conditions]
•
The chip is reset, or enters standby mode or module stop mode
•
Software reads ERS while it is set to 1, then writes 0.
1 Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
426
6 5
RDRF ORER
0 0
R/(W) * R/(W) * R/(W) *
Error signal status (ERS)
Status flag indicating that an error
signal has been received
4 3
ERS PER TEND
0 0
R/(W) *
Transmit end
Status flag indicating end
of transmission
2 1 0
MPB MPBT
1 0 0
R R R/W
(Initial value)