Duty Adjustment Circuit; Prescalers; Frequency Divider; Figure 20.6 External Clock Input Timing - Hitachi H8/3062 Hardware Manual

EXTAL
V
CC
V
STBY
IH
EXTAL
φ (internal or
external)
RES

Figure 20.7 External Clock Output Settling Delay Timing

20.3

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
20.4

Prescalers

The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
20.5

Frequency Divider

The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
632
t
EXH
t
EXr

Figure 20.6 External Clock Input Timing

t
DEXT
t
EXL
× 0.7
V
CC
0.3 V
t
EXf
× 0.5
V
CC