Table 22.8 Timing of On-Chip Supporting Modules
Condition:
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Condition A: V
= 2.7 to 5.5 V, AV
CC
Condition B: V
= 3.0 to 5.5 V, AV
CC
Condition C: V
= 5.0 V ± 10%, AV
CC
Module Item
Ports
Output data
and
delay time
TPC
Input data setup
time
Input data hold
time
16-bit
Timer output
timer
delay time
Timer input
setup time
Timer clock
input setup time
Timer
Single
clock
edge
pulse
Both
width
edges
8-bit
Timer output
timer
delay time
Timer input
setup time
Timer clock
input setup time
Timer
Single
clock
edge
pulse
Both
width
edges
668
= 2.7 to 5.5 V, V
CC
= 3.0 to 5.5 V, V
CC
= 5.0 V ± 10%, V
CC
A
Symbol
Min
Max
t
—
100
PWD
t
50
—
PRS
t
50
—
PRH
t
—
100
TOCD
t
50
—
TICS
t
50
—
TCKS
t
1.5
—
TCKWH
t
2.5
—
TCKWL
t
—
100
TOCD
t
50
—
TICS
t
50
—
TCKS
t
1.5
—
TCKWH
t
2.5
—
TCKWL
= –40°C to +85°C (wide-range
a
= 2.7 to AV
REF
= 3.0 to AV
REF
= 4.5 to AV
REF
Condition
B
C
Min
Max
Min
Max
—
100
—
50
50
—
50
—
50
—
50
—
—
100
—
50
50
—
50
—
50
—
50
—
1.5
—
1.5
—
2.5
—
2.5
—
—
100
—
50
50
—
50
—
50
—
50
—
1.5
—
1.5
—
2.5
—
2.5
—
, V
= AV
= 0 V
CC
SS
SS
, V
= AV
= 0 V
CC
SS
SS
, V
= AV
= 0 V
CC
SS
SS
Test
Unit
Conditions
ns
Figure 22.27
ns
ns
ns
Figure 22.28
ns
ns
Figure 22.29
t
cyc
t
cyc
ns
Figure 22.28
ns
ns
Figure 22.29
t
cyc
t
cyc