Figure 12.17 Example Of Sci Transmit Operation - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer h8/3062 series; h8/3062b series; h8/3062f-ztat series; h8/3064f-ztat series
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In transmitting serial data, the SCI operates as follows.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin in order from LSB (bit 0) to MSB (bit 7).
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI
loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE
flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the
TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is
requested at this time.
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 12.17 shows an example of SCI transmit operation.
Serial clock
Serial data
TDRE
TEND
TXI interrupt
request
• Receiving Serial Data (Synchronous Mode): Figure 12.18 shows a sample flowchart for
receiving serial data and indicates the procedure to follow. When switching from
asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are cleared
to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and
receiving will be disabled.
410
Transmit direction
Bit 0
Bit 1
TXI interrupt handler
TXI interrupt
writes data in TDR
request
and clears TDRE
flag to 0
1 frame

Figure 12.17 Example of SCI Transmit Operation

Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TEI interrupt
request

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