Figure 22.24 Basic Bus Cycle: Three-State Access - Hitachi H8/3062 Hardware Manual

φ
A to A ,
23 0
CS
n
AS
RD
(read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
758
T
1
t
ACC2
t
WSD
t
AS2
t
WDD

Figure 22.24 Basic Bus Cycle: Three-State Access

T T
2 3
t
ACC4
t
ACC4
t
RDS
t
WSW2
t
WDS2