Figure 6.12 Bus Control Signal Timing For 16-Bit, Three-State-Access Area - Hitachi H8/3062 Hardware Manual

Address bus
Read access
Write access
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
152
T
φ
CS
n
AS
RD
D to D
15 8
D to D
7 0
HWR
LWR
D to D
15 8
D to D
7 0
(Word Access)
Bus cycle
T
1 2
External address in area n
Valid
Valid
T
3
Valid
Valid