Table 1.1 Features - Hitachi H8/3062 Hardware Manual

Table 1.1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
High-speed operation
H8/3062F-ZTAT
H8/3062F-ZTAT R-Mask version
H8/3062 (mask ROM version)
H8/3061 (mask ROM version)
H8/3060 (mask ROM version)
H8/3064F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
H8/3064 mask ROM B-mask version
H8/3062 mask ROM B-mask version
H8/3061 mask ROM B-mask version
H8/3060 mask ROM B-mask version
16-Mbyte address space
Instruction features
•
•
•
•
•
2
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
Maximum Add/
clock rate subtract
20 MHz 100 ns
25 MHz 80 ns
Multiply/
divide
700 ns
560 ns