Figure 8.2 Block Diagram Of Channels 0 And 1 - Hitachi H8/3062 Hardware Manual

Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.
Both have the structure shown in figure 8.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Legend:
16TCNT : Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits × 2)
GRA, GRB :
TCR : Timer control register (8 bits)
TIOR : Timer I/O control register (8 bits)
224
Clock selector
Comparator

Figure 8.2 Block Diagram of Channels 0 and 1

Control logic
Module data bus
TIOCA
0
TIOCB
0
IMIA0
IMIB0
OVI0