Bus Control Register (Bcr) - Hitachi H8/3062 Hardware Manual

Bit 5—Address 21 Enable (A21E): Enables PA
Writing 0 in this bit enables A
be modified and PA
6
Bit 5
A21E Description
0 PA
1 PA
Bit 4—Address 20 Enable (A20E): Enables PA
Writing 0 in this bit enables A
Bit 4
A20E Description
0 PA
1 PA
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE Description
0 The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
1 The bus can be released to an external device
6.2.5

Bus Control Register (BCR)

7
Bit
ICIS1
Initial value 1
Read/Write R/W
Note: * 1 must not be written in bits 5 to 3.
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables WAIT pin input.
output from PA
21
has its ordinary port functions.
is the A address output pin
6 21
is an input/output pin
6
output from PA
20
is the A address output pin (Initial value when in mode 3 or 4)
7 20
is an input/output pin (Initial value when in mode 1, 2, 5, 6 or 7)
7
6 5
ICIS0 —
1 0*
R/W —
to be used as the A
6
. In modes other than 3, 4, and 5, this bit cannot
6
to be used as the A
7
. This bit can only be modified in mode 5.
7
4 3
—
—
0* 0*
— —
address output pin.
21
(Initial value)
address output pin.
20
(Initial value)
2 1
— RDEA WAITE
1 1
— R/W
0
0
R/W
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