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Increment
address
Notes: *1 Prewriting (setting erase block data to all 0s) is not necessary.
*2 Verify data is read in 16-bit (word) units.
*3 Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
*4 Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
*5 The wait times and the value of N are shown in section 22.3.6, Flash Memory Characteristics.
Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Start
*1
Set SWE bit in FLMCR1
) µs
Wait (t
sswe
n = 1
Set EBR1 or EBR2
Enable WDT
Set ESU bit in FLMCR1
) µs
Wait (t
sesu
Set E bit in FLMCR1
Wait (t
) ms
se
Clear E bit in FLMCR1
) µs
Wait (t
ce
Clear ESU bit in FLMCR1
) µs
Wait (t
cesu
Disable WDT
Set EV bit in FLMCR1
) µs
Wait (t
sev
Set block start address as verify address
H'FF dummy write to verify address
) µs
Wait (t
sevr
Read verify data
Verify data = all 1s?
Yes
No
Last address of block?
Yes
Clear EV bit in FLMCR1
) µs
Wait (t
cev
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
End of erasing
Perform erasing in block units.
*5
*3 , *4
*5
Start of erase
*5
End of erase
*5
*5
*5
*5
*2
No
Clear EV bit in FLMCR1
) µs
Wait (t
*5
cev
n ≥ N?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
*5
cswe
Erase failure
n ← n + 1
Re-erase
*5
*5
No
*5
557
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