Bus Release Control Register (Brcr) - Hitachi H8/3062 Hardware Manual

6.2.4

Bus Release Control Register (BRCR)

BRCR is an 8-bit readable/writable register that enables address output on bus lines A
enables or disables release of the bus to an external device.
Bit
Modes
Initial value
1, 2, 6,
and 7 Read/Write
Initial value
Modes
3 and 4
Read/Write
Initial value
Mode 5
Read/Write
BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset
and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA
Writing 0 in this bit enables A
be modified and PA
4
Bit 7
A23E Description
0 PA
1 PA
Bit 6—Address 22 Enable (A22E): Enables PA
Writing 0 in this bit enables A
be modified and PA
5
Bit 6
A22E Description
0 PA
1 PA
132
7 6
A23E A22E A21E
1 1
— —
1 1
R/W R/W R/W
1 1
R/W R/W R/W
Address 23 to 20 enable
These bits enable PA
used for A to A address output
23 20
output from PA
23
has its ordinary port functions.
is the A address output pin
4 23
is an input/output pin
4
output from PA
22
has its ordinary port functions.
is the A address output pin
5 22
is an input/output pin
5
5 4 3
A20E —
1 1 1
— — —
1 0 1
— —
1 1 1
R/W —
to PA to be
7 4
to be used as the A
4
. In modes other than 3, 4, and 5, this bit cannot
4
to be used as the A
5
. In modes other than 3, 4, and 5, this bit cannot
5
23
2 1
— —
1 1
— —
1 1
— —
1 1
— —
Reserved bits
Bus release enable
Enables or disables release
of the bus to an external device
address output pin.
23
(Initial value)
address output pin.
22
(Initial value)
to A and
20
0
BRLE
0
R/W
0
R/W
0
R/W