Timing Of Clearing Of Status Flags; Figure 8.35 Timing Of Setting Of Ovf; Figure 8.36 Timing Of Clearing Of Status Flags - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer h8/3062 series; h8/3062b series; h8/3062f-ztat series; h8/3064f-ztat series
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Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
8.5.2

Timing of Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.36 shows the timing.
φ
Address
IMF, OVF
270

Figure 8.35 Timing of Setting of OVF

T

Figure 8.36 Timing of Clearing of Status Flags

TISR write cycle
T
1
2
TISR address
T
3

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