Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the
T
state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.
3
Figure 8.38 shows the timing in this case.
φ
Address bus
Internal write signal
16TCNT input clock
16TCNT
Figure 8.38 Contention between 16TCNT Word Write and Increment
16TCNT word write cycle
T
T
1
2
16TCNT address
N
16TCNT write data
T
3
M
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