Table 22.56 Timing Of On-Chip Supporting Modules - Hitachi H8/3062 Hardware Manual

Table 22.56 Timing of On-Chip Supporting Modules

Condition: T = –20°C to +75°C (regular specifications),
a
T = –40°C to 85°C (wide-range specifications)
a
Condition A: V = 5.0 V ± 10%, AV
CC
fmax = 20 MHz
Condition B: V = 5.0 V ± 10%, AV
CC
fmax = 25 MHz
Module Item
Ports Output data delay time
and TPC Input data setup time
Input data hold time
16-bit Timer output delay time
timer
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width Both edges
8-bit Timer output delay time
timer
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width Both edges
SCI Input clock Asyn- chronous
cycle
Input clock rise time
Input clock fall time
Input clock
pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive
data hold
time (syn-
chronous)
= 5.0 V ± 10%, V
CC
= 5.0 V ± 10%, V
CC
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
t
TCKWH
t
TCKWL
t
TOCD
t
TICS
t
TCKS
t
TCKWH
t
TCKWL
t
Scyc
Syn- chronous
t
SCKr
t
SCKf
t
SCKW
t
TXD
t
RXS
Clock input t
RXH
Clock output
= 4.5 to AV
REF CC
= 4.5 to AV
REF CC
Condition
A and B
Min Max Unit
— 50 ns
50 — ns
50 — ns
— 50 ns
50 — ns
50 — ns
1.5 — t
cyc
2.5 — t
cyc
— 50 ns
50 — ns
50 — ns
1.5 — t
cyc
2.5 — t
cyc
4 — t
cyc
6 — t
cyc
1.5 — t
cyc
1.5 — t
cyc
0.4 0.6 t
Scyc
— 100 ns
100 — ns
100 — ns
0 — ns
, V = AV = 0 V,
SS SS
, V = AV = 0 V,
SS SS
Test
Conditions
Figure 22.27
Figure 22.28
Figure 22.29
Figure 22.28
Figure 22.29
Figure 22.30
Figure 22.31
749