Figure 17.13 Flash Memory State Transitions (Modes 5 And 7 (On-Chip Rom Enabled), High Level Applied To Fwe Pin) - Hitachi H8/3062 Hardware Manual

*2 For details of FLER bit setting conditions, see section 17.3.4, Flash Memory Status
Register (FLMSR).
*3 FLMCR and EBR can be written to. However, registers will be initialized if a transition
is made to software standby mode in the error protection state.
Memory read verify
RD VF PR ER FLER = 0
P = 1 or
E = 1 P = 0 and
E = 0
Program mode
Erase mode
RD VF PR ER FLER = 0
Error
occurrence
Error protection mode
RD VF PR ER FLER= 1
RD : Memory read possible
VF : Verify-read possible
PR : Programming possible
ER : Erasing possible
Figure 17.13 Flash Memory State Transitions (Modes 5 and 7 (On-Chip ROM Enabled),
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.
mode
Reset release
and hardware
standby release and
software standby release
Reset or hardware standby
Error occurrence
(software standby)
Software
standby mode
Software standby
mode release
RD : Memory read not possible
VF : Verify-read not possible
PR : Programming not possible
ER : Erasing not possible
INIT : Register (FLMCR, EBR) initialization state
High Level Applied to FWE Pin)
Reset or hardware
standby or software
standby
(hardware protection)
RD VF PR ER INIT FLER = 0
Reset or hardware
standby
Reset or hardware
standby
Error protection mode
(software standby)
RD VF PR ER INIT FLER = 1
Reset or standby
509