Compare Match Timing; Figure 9.9 Count Timing For External Clock Input (Both-Edge Detection); Figure 9.10 Timing Of Timer Output - Hitachi H8/3062 Hardware Manual

φ
External clock input
8TCNT input clock
N–1 N N+1
8TCNT

Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection)

9.4.2

Compare Match Timing

Timer Output Timing: When compare match A or B occurs, the timer output is as specified by
the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Figure 9.10 shows the timing when the output is set to toggle on compare match A.
φ
Compare match A
signal
Timer output

Figure 9.10 Timing of Timer Output

304