Hitachi F-ZTAT H8/3039 Series Hardware Manual

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Hitachi Single-Chip Microcomputer

ADE-602-131A

Rev. 2.0

1/12/98

Hitachi,Ltd

H8/3039 Series

H8/3039, H8/3038

H8/3037, H8/3036

H8/3039 F-ZTAT

Hardware Manual

Table of Contents

Summary of Contents for Hitachi F-ZTAT H8/3039 Series

Page 1 Hitachi Single-Chip Microcomputer H8/3039 Series H8/3039, H8/3038 H8/3037, H8/3036 H8/3039 F-ZTAT Hardware Manual ADE-602-131A Rev. 2.0 1/12/98 Hitachi,Ltd...
Page 2 Preface The H8/3039 Series comprises high-performance single-chip microcomputers (MCUs) that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.
Page 3: Table Of Contents
Contents Section 1 Overview ......................Overview..........................Block Diagram........................Pin Description ........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................Pin Functions ........................Section 2 ........................15 Overview..........................15 2.1.1 Features ........................ 15 2.1.2 Differences from H8/300 CPU................CPU Operating Modes ...................... 17 Address Space........................
Page 4 2.9.1 Overview ......................52 2.9.2 On-Chip Memory Access Timing ................ 52 2.9.3 On-Chip Supporting Module Access Timing............53 2.9.4 Access to External Address Space ............... 54 Section 3 MCU Operating Modes ................Overview..........................55 3.1.1 Operating Mode Selection..................55 3.1.2 Register Configuration ..................
Page 5 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........5.2.3 IRQ Status Register (ISR) ..................91 5.2.4 IRQ Enable Register (IER) .................. 92 5.2.5 IRQ Sense Control Register (ISCR)..............Interrupt Sources........................ 94 5.3.1 External Interrupts....................94 5.3.2 Internal Interrupts ....................95 5.3.3 Interrupt Vector Table ..................
Page 6 7.2.3 Pin Functions in Each Mode ................137 Port 2..........................139 7.3.1 Overview ......................139 7.3.2 Register Descriptions.................... 140 7.3.3 Pin Functions in Each Mode ................142 7.3.4 Input Pull-Up Transistors ..................144 Port 3..........................145 7.4.1 Overview ......................145 7.4.2 Register Descriptions....................
Page 7 8.1.3 Input/Output Pins....................193 8.1.4 Register Configuration ..................195 Register Descriptions......................198 8.2.1 Timer Start Register (TSTR)................198 8.2.2 Timer Synchro Register (TSNC)................199 8.2.3 Timer Mode Register (TMDR) ................201 8.2.4 Timer Function Control Register (TFCR)............204 8.2.5 Timer Output Master Enable Register (TOER)............ 206 8.2.6 Timer Output Control Register (TOCR) ..............
Page 8 9.2.2 Port A Data Register (PADR) ................289 9.2.3 Port B Data Direction Register (PBDDR)............290 9.2.4 Port B Data Register (PBDR)................290 9.2.5 Next Data Register A (NDRA) ................291 9.2.6 Next Data Register B (NDRB) ................293 9.2.7 Next Data Enable Register A (NDERA)..............
Page 9 11.1.4 Register Configuration ..................330 11.2 Register Descriptions......................331 11.2.1 Receive Shift Register (RSR)................331 11.2.2 Receive Data Register (RDR) ................331 11.2.3 Transmit Shift Register (TSR)................332 11.2.4 Transmit Data Register (TDR) ................332 11.2.5 Serial Mode Register (SMR)................333 11.2.6 Serial Control Register (SCR)................
Page 10 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..........415 13.2.2 A/D Control/Status Register (ADCSR)..............416 13.2.3 A/D Control Register (ADCR)................419 13.3 CPU Interface ........................420 13.4 Operation ........................... 421 13.4.1 Single Mode (SCAN = 0) ..................421 13.4.2 Scan Mode (SCAN = 1) ..................
Page 11 15.6.4 NMI Input Disable Conditions ................469 15.7 Flash Memory Emulation by RAM ................... 470 15.8 Flash Memory PROM Mode ..................... 471 15.8.1 PROM Mode Setting.................... 471 15.8.2 Memory Map......................471 15.8.3 PROM Mode Operation ..................472 15.8.4 Memory Read Mode..................... 474 15.8.5 Auto-Program Mode ....................
Page 12 17.4.5 Usage Note ......................510 17.5 Hardware Standby Mode ....................511 17.5.1 Transition to Hardware Standby Mode ..............511 17.5.2 Exit from Hardware Standby Mode ..............511 17.5.3 Timing for Hardware Standby Mode ..............511 17.6 Module Standby Function....................512 17.6.1 Module Standby Timing..................
Page 13 Port 3 Block Diagram......................657 Port 5 Block Diagram......................658 Port 6 Block Diagram......................659 Port 7 Block Diagram......................661 Port 8 Block Diagram......................662 Port 9 Block Diagram......................664 Port A Block Diagram ....................... 668 C.10 Port B Block Diagram ....................... 671 Appendix DPin States ......................
Page 14: Overview
1.1 Overview The H8/3039 Series comprises microcomputers (MCUs) that integrate system supporting functions together with an H8/300H CPU core featuring an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.
Page 15 Table 1-1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 18 MHz • Add/subtract: 111 ns •...
Page 16 Table 1-1 Features (cont) Feature Description • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 16-bit integrated pulse inputs timer unit (ITU) • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) •...
Page 17 Table 1-1 Features (cont) Feature Description • Sleep mode Power-down • Software standby mode state • Hardware standby mode • Module standby function • Programmable System clock frequency division • On-chip clock oscillator Other features Product lineup Model (5V) Model (3V)* Package HD64F3039F HD64F3039VF...
Page 18: Block Diagram
1.2 Block Diagram Figure 1-1 shows an internal block diagram of the H8/3039 Series. Port 3 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL ø H8/300H CPU STBY RESO/FWE* Interrupt controller (Flash memory, masked ROM) /WAIT Watchdog timer (WDT) Serial 16-bit...
Page 19: Pin Description
1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3039 Series. TIOCA TIOCB TIOCA TIOCB RESO/FWE* TOCXA TOCXB ADTRG/TP XTAL Top view EXTAL (FP-80A, TFP-80C) /SCK STBY ø /WAIT Note: * Masked ROM: RESO Flash memory: FWE Figure 1-2 Pin Arrangement (FP-80A, TFP-80C Top View)
Page 20: Pin Functions
1.3.2 Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in each mode. Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Fl ash memor y...
Page 21 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Fl ash memor y /WAIT /WAIT /WAIT ø ø ø ø ø STBY STBY STBY STBY STBY...
Page 22 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Fl ash memor y EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL XTAL XTAL XTAL XTAL XTAL XTAL RESO/ RESO/...
Page 23 Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont) Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Fl ash memor y TIOCB TIOCB TIOCB TIOCB TIOCB TCLKD TCLKD TCLKD TCLKD TCLKD TIOCA TIOCA TIOCA TIOCA...
Page 24: Pin Functions
1.4 Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Type Symbol Pin No. Name and Function Power Input Power: For connection to the power supply. Connect all V pins to the system power supply. Input Ground: For connection to ground (0 V). Connect all V pins to the 0-V system power supply.
Page 25 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function System Input Reset input: When driven low, this pin control resets the chip RESO/ Output/ Reset output (Masked ROM version): Input Outputs WDT-generated reset signal to an external device. Write enable signal (F-ZTAT version): Flash memory write control signal.
Page 26 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function Programm- 8, 6 to 1 Output TPC output 15, 13 to 0 : Pulse output able timing 80 to 73 pattern controller (TPC) Serial com- 70, 9 Output Transmit data:(channels 0 and 1): SCI data output munication...
Page 27 Table 1-3 Pin Functions (cont) Type Symbol Pin No. Name and Function I/O ports 72, 11 Input/ Port 9: Six input/output pins. The direction 71, 10 output of each pin can be selected in the port 9 70, 9 data direction register (P9DDR). 80 to 73 Input/ Port A: Eight input/output pins.
Page 28: Cpu
Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 29: Differences From H8/300 Cpu
• High-speed operation  All frequently-used instructions execute in two to four states  Maximum clock frequency: 18 MHz  8/16/32-bit register-register add/subtract: 111 ns  8 × 8-bit register-register multiply: 778 ns  16 ÷ 8-bit register-register divide: 778 ns ...
Page 30: Cpu Operating Modes
2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1. Unless specified otherwise, all descriptions in this manual refer to advanced mode. Maximum 64 kbytes, program Normal mode and data areas combined...
Page 31: Address Space
2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of a normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address space depending on the MCU operation mode. Figure 2-2 shows the address ranges of the H8/3039 Series.
Page 32: Register Configuration
2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 33: General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 34: Control Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR).
Page 35: Initial Cpu Register Values
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
Page 36: Data Formats
2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 37: Memory Data Formats
General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory.
Page 38 Data Type Address Data Format 1-bit data Address Byte data Address Word data Address 2m Address 2m + 1 Address 2n Longword data Address 2n + 1 Address 2n + 2 Address 2n + 3 Figure 2-8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 39: Instruction Set
2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified as shown in table 2-1. Table 2-1 Instruction Classification Function Instruction Types Data transfer MOV, PUSH* , POP* , MOVTPE* , MOVFPE* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU...
Page 40: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction #xx Rn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 Implied Data BWL BWL BWL BWL BWL BWL BWL —...
Page 41 Table 2-2 Instructions and Addressing Modes (cont) Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction #xx Rn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 Implied System TRAPA — — — — — — — — — — — — control —...
Page 42: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined as follows. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand (EAs)
Page 43 Table 2-3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3039 Series.
Page 44 Table 2-4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 45 Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 46 Table 2-5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 47 Table 2-7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 48 Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ [¬ (<bit-No.> of <EAd>)] → C BIOR ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 49 Table 2-8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 50 Table 2-9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 51 Table 2-10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 52: Basic Instruction Formats
2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 53: Notes On Use Of Bit Manipulation Instructions
2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Page 54 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Page 55 Table 2-12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 16-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1,048,320 to 1,048,575) (16,776,960 to 16,777,215) 16 bits (@aa:16) H'00000 to H'07FFF, H'000000 to H'007FFF, H'F8000 to H'FFFFF H'FF8000 to H'FFFFFF (0 to 32,767, 1,015,808 to 1,048,575) (0 to 32,767, 16,744,448 to 16,777,215 24 bits (@aa:24)
Page 56: Effective Address Calculation
Reserved Specified by @aa:8 Branch address Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address.
Page 57 Table 2-13 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Effective Address Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) General register contents Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) General register contents disp Sign extension disp...
Page 58 Table 2-13 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Effective Address Absolute address @aa:8 H'FFFF 16 15 Sign @aa:16 extension @aa:24 Immediate Operand is immediate data #xx:8, #xx:16, or #xx:32 Program-counter relative @(d:8, PC) or @(d:16, PC) PC contents Sign disp...
Page 59 Table 2-13 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Effective Address Memory indirect @@aa:8 Normal mode H'0000 16 15 Memory contents H'00 Advanced mode H'0000 Memory contents Legend r, rm, rn: Register field Operation field disp: Displacement IMM:...
Page 60: Processing States
2.8 Processing States 2.8.1 Overview The H8/300H CPU has four processing states: the program execution state, exception-handling state, power-down state, and reset state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states. Figure 2-13 indicates the state transitions.
Page 61: Program Execution State
2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 62 Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources Program execution state SLEEP instruction with SSBY = 0 Exception End of exception Sleep mode handling SLEEP instruction Interrupt with SSBY = 1 NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state...
Page 63: Exception-Handling Sequences
2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 64: Reset State
2.8.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high.
Page 65: Basic Operational Timing
2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 66: On-Chip Supporting Module Access Timing
ø Address bus Address RD WR High High impedance to D Figure 2-16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed.
Page 67: Access To External Address Space
ø Address bus Address RD WR High High impedance to D Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area accessed in two or three states.
Page 68: Mcu Operating Modes
Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3039 Series has five operating modes (modes 1, 3, 5 to7) that are selected by the mode pins (MD and MD ) as indicated in table 3-1. The input at these pins determines expanded mode or single-chip mode.
Page 69: Register Configuration
Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 6 is a normal mode with 64-kbyte address space. Mode 7 is an advanced mode with a maximum address space of 1 Mbyte. The H8/3039 Series can be used only in modes 1, 3, or 5 to 7.
Page 70: Mode Control Register (Mdcr)
3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3039 Series. — — — — — MDS2 MDS1 MDS0 Initial value — — — Read/Write — — — — — Reserved bits Mode select 2 to 0 Bits indicating the current...
Page 71: System Control Register (Syscr)
3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3039 Series. SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select Selects the valid edge of the NMI input User bit enable...
Page 72 Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Page 73: Operating Mode Descriptions
3.4 Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A to A , permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. 3.4.2 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A to A...
Page 74: Pin Functions In Each Operating Mode
3.5 Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, port 5 and port A vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Mode 1 Mode 2*...
Page 75 Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000 Area 1 Area 2 H'5FFFF...
Page 76 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'07FFF H'F70F H'1FFFF H'F710 Area 0...
Page 77 Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000 Area 1 Area 2 H'5FFFF...
Page 78 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'F70F H'07FFF H'08000 H'F710 H'0FFFF...
Page 79 Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000 Area 1 Area 2 H'5FFFF...
Page 80 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'7FFF H'07FFF H'08000 H'FB10 Reserved...
Page 81 Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000 H'40000 Area 1 Area 2 H'5FFFF...
Page 82 Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'03FFF H'03FFF H'07FFF H'3FFF H'FD10 Reserved...
Page 83: Restrictions On Use Of Mode 6
3.7 Restrictions on Use of Mode 6 In mode 6 (single-chip normal mode), on-chip ROM area data is undefined if address H'10000 or above (64 kbytes or above) is accessed, and therefore instruction code fetch and data read operations may not always be performed normally. However, there is no problem with address H'10000 and above if the lower 16-bit address is an on-chip RAM (H'F710 to H'FF0F) or internal I/O register (H'FF1C to H'FFFF) address.
Page 84 Table 3-4 Access Restrictions in Mode 6 (Single-Chip Normal Mode) (cont) Conditions Addressing Mode Restricted Item Address Range Operation Restriction Absolute address Value of @aa Read data is Do not access addresses H'010000 or above, with lower 16 bits in (@aa:24) undefined.
Page 85: Exception Handling
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 86: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ , IRQ , IRQ , IRQ Exception •...
Page 87 Table 4-2 Exception Vector Table Vector Address* Exception Source Vector Number Normal Mode Advanced Mode Reset H'0000 to H'0001 H'0000 to H'0003 Reserved for system use H'0002 to H'0003 H'0004 to H'0007 H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F H'0008 to H'0009 H'0010 to H'0013...
Page 88: Reset
4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the H8/3039 Series enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
Page 89 Prefetch of Internal first program Vector fetch processing instruction ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit width) (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) Start address First instruction of program...
Page 90: Interrupts After Reset
4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends.
Page 91: Trap Instruction
4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code.
Page 92: Notes On Stack Usage
4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3039 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @–SP)
Page 93: Interrupt Controller
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 94: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend Interrupt mask bit IER: IRQ enable register Interrupt priority register A IPRA: IPRB:...
Page 95: Pin Configuration
5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable , IRQ External interrupt Input Maskable interrupts, falling edge or level and IRQ , IRQ request 5, 4, 1, and 0 sensing selectable...
Page 96 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR).
Page 97 Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 98 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 —...
Page 99 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit7 IPRA7 Description IRQ0 interrupt requests have priority level 0 (low priority) (Initial value) IRQ0 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests. Bit6 IPRA6 Description...
Page 100 Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests. Bit1 IPRA1 Description ITU channel 1 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 1 interrupt requests have priority level 1 (high priority) Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Page 101 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 IPRB2 IPRB1 — Initial value Read/Write — — — Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2...
Page 102 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit7 IPRB7 Description ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 3 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Page 103 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ , IRQ , IRQ , and IRQ interrupt requests. — — IRQ5F IRQ4F — — IRQ1F IRQ0F Initial value Read/Write — — R/(W)* R/(W) * —...
Page 104 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ , IRQ , IRQ , and IRQ interrupt requests. — — IRQ5E IRQ4E — — IRQ1E IRQ0E Initial value Read/Write — — Reserved bits Reserved bits IRQ to IRQ enable IRQ to IRQ enable...
Page 105: Irq Sense Control Register (Iscr)
5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ , IRQ , IRQ , and IRQ — — IRQ5SC IRQ4SC — — IRQ1SC IRQ0SC Initial value Read/Write Reserved bits...
Page 106: Interrupt Sources
5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ , IRQ , IRQ and IRQ ) and 25 internal interrupts. 5.3.1 External Interrupts There are five external interrupts: NMI, and IRQ , IRQ , IRQ , and IRQ .
Page 107: Internal Interrupts
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Note: n = 5, 4, 1 and 0 Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ , IRQ , IRQ , IRQ have vector numbers 17, 16, 13, 12.
Page 108 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Normal Mode Advanced Mode Priority External pins H'000E to H'000F H'001C to H'001F — High H'0018 to H'0019 H'0030 to H'0033 IPRA7 H'001A to H'001B H'0034 to H0037 IPRA6 Reserved —...
Page 109 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Vector Address* Vector Interrupt Source Origin Number Normal Mode Advanced Mode Priority IMIA3 (compare match/ ITU channel 3 H'0048 to H'0049 H'0090 to H'0093 IPRB7 input capture A3) IMIB3 (compare match/ H'004A to H'004B H'0094 to H'0097 input capture B3)
Page 110: Interrupt Operation
5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3039 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 111 Program execution state Interrupt requested? Pending Priority level 1? I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1...
Page 112 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 113 ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example) Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 114 Program execution state Interrupt requested? Pending Priority level 1? I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0...
Page 115: Interrupt Sequence
5.4.2 Interrupt Sequence Figure 5-7 shows the interrupt sequence in mode 5 when the program code and stack are in an on- chip memory area. Figure 5-7 Interrupt Sequence (Mode 5, Stack in On-Chip Memory)
Page 116: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory On-Chip 8-Bit Bus Item Memory 2 States 3 States...
Page 117: Usage Notes
5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 118: Instructions That Inhibit Interrupts
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 119 2 Generation conditions (1) A read of the ISR register is executed to clear the IRQaF flag while it is set to 1, then the IRQbF flag is cleared by the execution of interrupt exception handling. (2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag setting). (IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1 before ISR is written to.) If the above setting conditions (1) to (3) and generation conditions (1) and (3)are all fulfilled,...
Page 120 Method 1 When clearing the IRQaF flag, read ISR as a byte unit instead of using a bit-manipulation instruction, and write a byte value that clears the IRQaF flag to 0 and sets the other bits to 1. Example: When a = 0 MOV.B @ISR, R0L MOV.B #HFE, R0L MOV.B R0L, @ISR...
Page 121: Bus Controller
Section 6 Bus Controller 6.1 Overview The H8/3039 Series has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. 6.1.1 Features Features of the bus controller are listed below.
Page 122: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. ASTCR Internal WCER address bus Area Internal signals decoder Access state control signal Bus control Wait request signal circuit Wait-state WAIT controller Legend ASTCR: Access state control register WCER: Wait state controller enable register WCR:...
Page 123: Input/Output Pins
6.1.3 Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Abbreviation Function Address strobe Output Strobe signal indicating valid address output on the address bus Read Output Strobe signal indicating reading from the external address space Write Output...
Page 124: Register Descriptions
6.2 Register Descriptions 6.2.1 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 125: Wait Control Register (Wcr)
6.2.2 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. — — — — WMS1 WMS0 Initial value Read/Write — — — —...
Page 126: Wait State Controller Enable Register (Wcer)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit1 Bit0 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.3 Wait State Controller Enable Register (WCER)
Page 127: Address Control Register (Adrcr)
6.2.4 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21. — — — — — Initial value Mode 1 and 5 to 7 Read/Write — — — — — —...
Page 128 Bit 5—Address 21 Enable (A E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A address output from PA . In modes other than 3 this bit cannot be modified and PA has its ordinary input/output functions.
Page 129: Operation
6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6-2 shows a general view of the memory map.
Page 130 The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ASTCR WCER Bus Specifications Access ASTn WCEn WMS1 WMS0 Width States Wait Mode — — — Disabled —...
Page 131: Bus Control Signal Timing
6.3.2 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit, three-state-access area. Wait states can be inserted. Bus cycle ø Address bus External address Read access Valid to D Write access Valid to D...
Page 132 8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait states cannot be inserted. Bus cycle ø Address bus External address Read access to D Valid Write access to D Valid Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area...
Page 133: Wait Modes
6.3.3 Wait Modes Four wait modes can be selected for each area as shown in table 6-4. Table 6-4 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode — — — Disabled No wait states —...
Page 134 Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall ) is inserted. If the WAIT pin remains low, of the system clock (ø) in the T state, a wait state (T wait states continue to be inserted until the WAIT signal goes high.
Page 135 Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states ) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high.
Page 136 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T state, the number of wait states (T ) selected by bits WC1 and WC0 are inserted.
Page 137 Programmable Wait Mode: The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6-8 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø...
Page 138 Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6-9 shows an example of wait mode settings.
Page 139: Interconnections With Memory (Example)
6.3.4 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices. Figure 6-10 shows a memory map for this example. A 32-kword ×...
Page 140 H'00000 On-chip ROM Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 EPROM H'47FFF Area 2 H'48000 8-bit, three-state-access area Not used H'5FFFF H'60000 SRAM1, 2 Area 3 H'6FFFF 8-bit, two-state-access area H'70000 Not used H'7FFFF Areas 4, 5, 6 H'E0000 SRAM3 H'E7FFF Area 7...
Page 141: Usage Notes
6.4 Usage Notes 6.4.1 Register Write Timing ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 2 changes area 2 from three-state access to two-state access. ø...
Page 142: I/O Ports
Section 7 I/O Ports 7.1 Overview The H8/3039 Series has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 7-1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7-1.
Page 143 Table 7-1 Port Functions Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O port to P1 Address output Address output Generic input/ output to A pins (A to A to A ) and •...
Page 144 Table 7-1 Port Functions (cont) Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 / I RQ Port 9 • 6-bit I/O / SCK Input and output (SCK , SCK , RxD , RxD , TxD , TxD / I RQ port...
Page 145 Table 7-1 Port Functions (cont) Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port B • 7-bit I/Oport TPC output (TP ), trigger input (ADTRG) to A/D ADTRG converter, and generic input/output. • Can drive LEDs TPC output (TP to TP...
Page 146: Port 1
7.2 Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), they are address bus output pins (A to A In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction...
Page 147 Table 7-2 Port 1 Registers Initial Value Address Name Abbreviation Modes 1, 3 Modes 5 to 7 H'FFC0 Port 1 data direction P1DDR H'FF H'00 register H'FFC2 Port 1 data register P1DR H'00 H'00 Note: Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1.
Page 148: Pin Functions In Each Mode
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 7.2.3 Pin Functions in Each Mode The pin functions of port 1 differ between mode 1, 3 (expanded mode with on-chip ROM disabled) , mode 5 (expanded mode with on-chip ROM enabled) , mode 6, and 7 (single-chip mode).
Page 149 When P1DDR = 1 When P1DDR = 0 A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) Port 1 A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) Figure 7-3 Pin Functions in Mode 5 (Port 1) Modes 6 and 7 (Single-Chip Mode): Input or output can be selected separately for each pin in...
Page 150: Overview
7.3 Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-5. Pin functions differ according to operation mode. In modes 1 and 3 (expanded mode with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 151: Register Descriptions
7.3.2 Register Descriptions Table 7-3 summarizes the registers of port 2. Table 7-3 Port 2 Registers Initial Value Address Name Abbreviation Modes 1 and 3 Modes 5 to 7 H'FFC1 Port 2 data direction P2DDR H'FF H'00 register H'FFC3 Port 2 data register P2DR H'00 H'00...
Page 152 Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores data for pins to P2 Initial value Read/Write Port 2 data 7 to 0 These bits store data for port 2 pins When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned directly, regardless of the actual state of the pin.
Page 153: Pin Functions In Each Mode
7.3.3 Pin Functions in Each Mode The pin functions of port 2 differ between mode 1, 3 (expanded mode with on-chip ROM disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described followings. Modes 1 and 3: Address output can be selected for each pin in port 2.
Page 154 When P2DDR = 1 When P2DDR = 0 (output) P2 (input) (output) P2 (input) (output) P2 (input) (output) P2 (input) Port 2 (output) P2 (input) (output) P2 (input) A (output) P2 (input) A (output) P2 (input) Figure 7-7 Pin Functions in Modes 1 and 3 (Port 2) Modes 6 and 7: Input or output can be selected separately for each pin in port 2.
Page 155 7.3.4 Input Pull-Up Transistors Port 2 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up transistor is turned on.
Page 156: Port 3
7.4 Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7-9. Port 3 is a data bus in modes 1, 3 and 5 (expanded modes) and a generic input/output port in mode 6 and 7 (single-chip mode).
Page 157 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 data direction 7 to 0...
Page 158 7.4.3 Pin Functions in Each Mode The pin functions of port 3 differ between modes 1, 3 and 5 and modes 6 and 7. The pin functions in each mode are described below. Modes 1, 3 and 5: All pins of port 3 automatically become data input/output pins. Figure 7-10 shows the pin functions in modes 1, 3 and 5.
Page 159: Port 5
7.5 Port 5 7.5.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7-12. The pin functions differ depending on the operating mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A19 to A16).
Page 160 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Modes 1 and 3 Read/Write —...
Page 161 Port 5 Input Pull-Up Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. — — — — P5 PCR P5 PCR P5 PCR P5 PCR Initial value Read/Write — — —...
Page 162 7.5.3 Pin Functions in Each Mode The pin functions differ between mode 1, 3 (expanded modes with on-chip ROM disabled), mode 5 (expanded modes with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described below. Modes 1 and 3: Address output can be selected for each pin in port 5.
Page 163 P5 (input/output) P5 (input/output) Port 5 P5 (input/output) P5 (input/output) Figure 7-15 Pin Functions in Mode 6 and 7 (Port 5) 7.5.4 Input Pull-Up Transistors Port 5 has built-in MOS pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually.
Page 164: Port 6
7.6 Port 6 7.6.1 Overview Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR, RD, AS, and WAIT). Figure 7-16 shows the pin configuration of port 6. In modes 1, 3 and 5, the pin functions are WR, RD, AS, and P6 /WAIT.
Page 165 Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. — — P6 DDR P6 DDR P6 DDR — — P6 DDR Initial value Read/Write — Reserved bits Port 6 data direction 5 to 3, 0 These bits select input or output for port 6 pins...
Page 166: Pin Functions In Each Mode
When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level is read.
Page 167 Table 7-9 Port 6 Pin Functions in Modes 1, 3, and 5 Pin Functions and Selection Method Functions as follows regardless of P6 WR output Pin function Functions as follows regardless of P6 RD output Pin function Functions as follows regardless of P6 AS output Pin function /WAIT...
Page 168 Modes 6 and 7: Input or output can be selected separately for each pin in port 6. A pin becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7-18 shows the pin functions in modes 6 and 7.
Page 169: Overview
7.7 Port 7 7.7.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin functions are the same in all operating modes. Figure 7-19 shows the pin configuration of port 7. Port 7 pins P7 (input)/AN (input) P7 (input)/AN (input)
Page 170: Overview
Port 7 Data Register (P7DR) Initial value — — — — — — — — Read/Write Note: * Determined by pins P7 to P7 .07Note: When port 7 is read, the pin levels are always read. 7.8 Port 8 7.8.1 Overview Port 8 is a 2-bit input/output port that is also used for IRQ and IRQ input.
Page 171 7.8.2 Register Descriptions Table 7-11 summarizes the registers of port 8. Table 7-11 Port 8 Registers Address* Name Abbreviation Initial Value H'FFCD Port 8 data direction register P8DDR H'E0 H'FFCF Port 8 data register P8DR H'E0 Note: * Lower 16 bits of the address. Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Page 172 Bits 7 to 2 are reserved. Bits 7 to 5 cannot be modified and always read 1. Bit 4, 3, and 2 can be written and read, but it cannot be used for port input or output. If bit 4, 3, and 2 of P8DDR is read while its value is 1, bit 4, 3 and 2 of P8DR is read directly.
Page 173: Overview
7.9 Port 9 7.9.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 174 Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. — — P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR Initial value Read/Write —...
Page 175 Table 7-14 Port 9 Pin Functions Pin Functions and Selection Method /SCK Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P9 select the pin function as follows CKE1 — CKE0 — — —...
Page 176 Table 7-14 Port 9 Pin Functions (cont) Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows — Pi n funct i on input output output /TxD Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows SMIF...
Page 177: Port A
7.10 Port A 7.10.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), and address output (A...
Page 178: Register Descriptions
7.10.2 Register Descriptions Table 7-15 summarizes the registers of port A. Table 7-15 Port A Registers Initial Value Address* Name Abbreviation Modes 1, 5, and 7 Mode 3 H'FFD1 Port A data direction PADDR H'00 H'80 register H'FFD3 Port A data register PADR H'00 H'00...
Page 179 Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for pins PA to PA Initial value Read/Write Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly.
Page 180: Pin Functions
7.10.3 Pin Functions The port A pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB to TIOCB TIOCA to TIOCA ) and input (TCLKD, TCLKC, TCLKB, TCLKA), and as address bus pins to A ). Table 7-16 describes the selection of pin functions. Table 7-16 Port A Pin Functions Pin Functions and Selection Method The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0...
Page 181 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method / TP The mode setting, bit A E in BRCR, ITU channel 2 settings (bit PWM2 in TMDR and TI OCA bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 182 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and TIOCB bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 183 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and TIOCB bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 184 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TIOCB TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in PADDR TCLKD select the pin function as follows channel 0...
Page 185 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TIOCA TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA DDR in PADDR TCLKC select the pin function as follows...
Page 186 Table 7-16 Port A Pin Functions (cont) Pin Functions and Selection Method Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function as follows TCLKB NDER1 — input output output function TCLKB input* Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
Page 187: Port B
7.11 Port B 7.11.1 Overview Port B is an 7-bit input/output port that is also used for TPC output (TP , TP to TP ), ITU input/output (TIOCB , TIOCB , TIOCA , TIOCA ) and ITU output (TOCXB , TOCXA ), and ADTRG input to the A/D converter.
Page 188 Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data 7, 5 to 0 These bits select input or output for port B pins...
Page 189: Pin Functions
When port B pins are used for TPC output, PBDR stores output data for TPC output groups 2 and 3. If a bit in the next data enable register (NDERB) is set to 1, the corresponding PBDR bit cannot be written. In this case, PBDR can be updated only when data is transferred from NDRB. 7.11.3 Pin Functions The port B pins are also used for TPC output (TP , TP...
Page 190 Table 7-18 Port B Pin Functions Pin Functions and Selection Method Bit TRGE in ADCR, bit NDER15 in NDERB and bit PB7DDR in PBDDR select the pin function as follows ADTRG NDER15 — input output output ADTRG input* function Notes: * ADTRG input when TRGE = 1. ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in NDERB, and bit PB DDR in PBDDR select the pin function as follows...
Page 191 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in PBDDR TIOCB select the pin function as follows...
Page 192 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR TIOCA select the pin function as follows...
Page 193 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER11 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 194 Table 7-18 Port B Pin Functions (cont) Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows channel 3...
Page 195: 16-Bit Integrated Timer Unit (Itu)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1 Overview The H8/3039 Series has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer channels. 8.1.1 Features ITU features are listed below. • Capability to process up to 12 pulse outputs or 10 pulse inputs •...
Page 196  Complementary PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms.  Buffering Input capture registers can be double-buffered. Output compare registers can be updated automatically. • High-speed access via internal 16-bit bus The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed via a 16-bit bus.
Page 197 Table 8-1 ITU Functions (cont) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Compare match output Toggle — Input capture function Synchronization PWM mode Reset-synchronized — — — PWM mode Complementary — — — PWM mode Phase counting —...
Page 198: Block Diagrams
8.1.2 Block Diagrams ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector IMIB0 to IMIB4 OVI0 to OVI4 ø, ø/2, ø/4, ø/8 TOCXA , TOCXB Control logic TIOCA to TIOCA TIOCB to TIOCB...
Page 199 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8-2. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA0 Comparator IMIB0 OVI0 Module data bus Legend TCNT:...
Page 200 Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB ø, ø/2, ø/4, ø/8 Control logic IMIA2 Comparator IMIB2 OVI2...
Page 201 Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector ø, ø/2, ø/4, ø/8 Control logic IMIA3 Comparator IMIB3 OVI3 Module data bus...
Page 202 TOCXA TCLKA to TOCXB TCLKD Clock selector ø, ø/2, TIOCA ø/4, ø/8 TIOCB Control logic IMIA4 Comparator IMIB4 OVI4 Module data bus Legend TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 203 8.1.3 Input/Output Pins Table 8-2 summarizes the ITU pins. Table 8-2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input External clock B input pin...
Page 204 Table 8-2 ITU Pins(cont) Abbre- Input/ Channel Name viation Output Function Input capture/output TIOCA Input/ GRA4 output compare or input capture pin compare A4 output PWM output pin in PWM mode, complementary PWM mode, or reset- synchronized PWM mode Input capture/output TIOCB Input/ GRB4 output compare or input capture pin...
Page 205: Register Configuration
8.1.4 Register Configuration Table 8-3 summarizes the ITU registers. Table 8-3 ITU Registers Abbre- Initial Channel Address* Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register TMDR H'80 H'FF63 Timer function control register TFCR H'C0...
Page 206 Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address* Name viation Value H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 H'FF7B Timer status register 2 TSR2 R/(W)* H'F8...
Page 207 Table 8-3 ITU Registers (cont) Abbre- Initial Channel Address* Name viation Value H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 H'FF95 Timer status register 4 TSR4 R/(W)* H'F8...
Page 208: Register Descriptions
8.2 Register Descriptions 8.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — —...
Page 209: Timer Synchro Register (Tsnc)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 Description TCNT1 is halted (Initial value) TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 Description STR0 TCNT0 is halted (Initial value) TCNT0 is counting...
Page 210 Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3 SYNC3 Description Channel 3’s timer counter (TCNT3) operates independently (Initial value) TCNT3 is preset and cleared independently of other channels Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously.
Page 211: Timer Mode Register (Tmdr)
8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. — FDIR PWM4 PWM3 PWM2 PWM1 PWM0...
Page 212 When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 213 Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3 PWM3 Description Channel 3 operates normally (Initial value) Channel 3 operates in PWM mode When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match with general register B3 (GRB3).
Page 214: Timer Function Control Register (Tfcr)
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. PWM0 Description Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match with general register B0 (GRB0).
Page 215 Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1. Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 Bit 4 CMD1...
Page 216: Timer Output Master Enable Register (Toer)
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 Description GRB3 operates normally (Initial value) GRB3 is buffered by BRB3 Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3.
Page 217 Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1. Bit 5—Master Enable TOCXB (EXB4): Enables or disables ITU output at pin TOCXB Bit 5 EXB4 Description TOCXB output is disabled regardless of TFCR settings (TOCXB operates as a generic input/output pin).
Page 218 Bit 1—Master Enable TIOCA (EA4): Enables or disables ITU output at pin TIOCA Bit 1 Description TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA operates as a generic input/output pin). If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1. TIOCA is enabled for output according to TIOR4, TMDR, and TFCR (Initial value)
Page 219: Timer Output Control Register (Tocr)
8.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — — — XTGD — — OLS4 OLS3 Initial value Read/Write —...
Page 220: Timer Counters (Tcnt)
Bits 3 and 2—Reserved: These bits cannot be modified and are always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description TIOCA , TIOCA , and TIOCB pin outputs are inverted TIOCA , TIOCA...
Page 221: General Registers (Gra, Grb)
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM mode and up-counters in other modes. TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or by input capture to GRA or GRB (counter clearing function) in the same channel.
Page 222: Buffer Registers (Bra, Brb)
When a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR.
Page 223: Timer Control Registers (Tcr)
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 8.2.10 Timer Control Registers (TCR) TCR is an 8-bit register.
Page 224 Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture* TCNT is cleared by GRB compare match or input capture* Synchronous clear: TCNT is cleared in synchronization with...
Page 225 Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: ø (Initial value) Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input...
Page 226: Timer I/O Control Register (Tior)
8.2.11 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The ITU has five TIORs, one in each channel. Channel Abbreviation Function TIOR0 TIOR controls the general registers. Some functions differ in PWM TIOR1 mode. TIOR3 and TIOR4 settings are ignored when complementary TIOR2 PWM mode or reset-synchronized PWM mode is selected in TIOR3...
Page 227 Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 Function GRB is an output No output at compare match (Initial value)
Page 228: Timer Status Register (Tsr)
8.2.12 Timer Status Register (TSR) TSR is an 8-bit register. The ITU has five TSRs, one in each channel. Channel Abbreviation Function TSR0 Indicates input capture, compare match, and overflow status TSR1 TSR2 TSR3 TSR4 — — — — — IMFB IMFA Initial value...
Page 229 Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1. Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow. Bit 2 Description [Clearing condition] (Initial value) Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF* Notes: *...
Page 230: Timer Interrupt Enable Register (Tier)
8.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function TIER0 Enables or disables interrupt requests. TIER1 TIER2 TIER3 TIER4 — — — — — OVIE IMIEB IMIEA Initial value Read/Write...
Page 231 Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1. Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the overflow flag (OVF) in TSR when OVF is set to 1. Bit 2 OVIE Description OVI interrupt requested by OVF is disabled...
Page 232: Cpu Interface
8.3 CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus.
Page 233 Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) Internal data bus Module Bus interface...
Page 234: 8-Bit Accessible Registers
Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8-12 and 8-13 show examples of byte read and write access to a TCR.
Page 235: Operation
8.4 Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 236: Basic Functions
When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register. • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction.
Page 237 Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 8-14 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal.
Page 238 • Free-running and periodic counter operation A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer status register (TSR).
Page 239 TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 8-16 Periodic Counter Operation • Count timing  Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Page 240  External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
Page 241 Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Page 242 TCNT value H'FFFF H'0000 Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 8-20 0 and 1 Output (Examples) Figure 8-21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B.
Page 243 • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 244 Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these TIOR settings. Select input-capture input Start counter Set the STR bit to 1 in TSTR to start the timer...
Page 245 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8-25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 246: Synchronization
8.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 247 Example of Synchronization: Figure 8-27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 248: Pwm Mode
8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
Page 249 Sample Setup Procedure for PWM Mode: Figure 8-28 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock select the desired edge(s) of the...
Page 250 Examples of PWM Mode: Figure 8-29 shows examples of operation in PWM mode. The PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB.
Page 251 Figure 8-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
Page 252: Reset-Synchronized Pwm Mode
8.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB and TOCXB...
Page 253 Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 8-31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 254 Example of Reset-Synchronized PWM Mode: Figure 8-32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with GRB3, GRA4, GRB4, and TCNT3 respectively, and when the counter is cleared.
Page 255: Complementary Pwm Mode
8.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB , and TOCXB automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down- counters.
Page 256 Setup Procedure for Complementary PWM Mode: Figure 8-33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are halted.
Page 257 Clearing Complementary PWM Mode: Figure 8-34 shows a sample procedure for clearing complementary PWM mode. Complementary PWM mode Clear bit CMD1 in TFCR to 0, and set channels 3 and 4 to normal operating Clear complementary mode mode. After setting channels 3 and 4 to normal operating mode, wait at least one clock count before clearing bits STR3 and Stop counting...
Page 258 Examples of Complementary PWM Mode: Figure 8-35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows.
Page 259 Figure 8-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3.
Page 260 In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ.
Page 261 Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 8-38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 262 GRA3 H'0000 Not allowed Figure 8-39 Changing a General Register Setting by Buffer Transfer (Example 1)  Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range.
Page 263  Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range.
Page 264  General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times.
Page 265: Phase Counting Mode
8.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 266 Example of Phase Counting Mode: Figure 8-44 shows an example of operations in phase counting mode. Table 8-9 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 267: Buffering
8.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next.
Page 268 • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times:  When TCNT3 matches GRA3  When TCNT4 underflows • Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3.
Page 269 Examples of Buffering: Figure 8-49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
Page 270 ø n + 1 TCNT Compare match signal Buffer transfer signal Figure 8-50 Compare Match and Buffer Transfer Timing (Example)
Page 271 Figure 8-51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA.
Page 272 ø TIOC pin Input capture signal TCNT n + 1 N + 1 Figure 8-52 Input Capture and Buffer Transfer Timing (Example)
Page 273 Figure 8-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 274: Itu Output Timing
8.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 275 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 8-55 shows the timing.
Page 276: Interrupts
8.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 277 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 8-58 shows the timing. ø Input capture signal TCNT Figure 8-58 Timing of Setting of IMFA and IMFB by Input Capture...
Page 278: Clearing Of Status Flags
ø TCNT H'FFFF H'0000 Overflow signal Figure 8-59 Timing of Setting of OVF 8.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
Page 279: Interrupt Sources
8.5.3 Interrupt Sources Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1.
Page 280: Usage Notes
8.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8-61.
Page 281 Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 8-62. TCNT word write cycle ø Address TCNT address Internal write signal TCNT input clock TCNT...
Page 282 Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 8-63, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 283 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8-64. General register write cycle ø...
Page 284 Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 8-65. TCNT write cycle ø...
Page 285 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8-66. General register read cycle ø Address GR address Internal read signal Input capture signal...
Page 286 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 287 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8-68. General register write cycle ø...
Page 288 Contention between Buffer Register Write and Input Capture: If a buffer register is used for input capture buffering and an input capture signal occurs in the T state of a write cycle, input capture takes priority and the write to the buffer register is not performed. See figure 8-69. Buffer register write cycle ø...
Page 289 Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized •...
Page 290 ITU Operating Modes Table 8-11 (a) ITU Operating Modes (Channel 0) Register Settings TSNC TMDR TFCR TOCR TOER TIOR0 TCR0 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset...
Page 291 Table 8-11 (b) ITU Operating Modes (Channel 1) Register Settings TSNC TMDR TFCR TOCR TOER TIOR1 TCR1 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC1 = 1 —...
Page 292 Table 8-11 (c) ITU Operating Modes (Channel 2) Register Settings TSNC TMDR TFCR TOCR TOER TIOR2 TCR2 Reset- Comple- Synchro- Output Synchro- mentary nized Buffer- Level Master Clear Clock Operating Mode nization FDIR PWM XTGD Select Enable IOA Select Select Synchronous preset SYNC2 = 1 —...
Page 293 Table 8-11 (d) ITU Operating Modes (Channel 3) Register Settings TSNC TMDR TFCR TOCR TOER TIOR3 TCR3 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC3 = 1 —...
Page 294 Table 8-11 (e) ITU Operating Modes (Channel 4) Register Settings TSNC TMDR TFCR TOCR TOER TIOR4 TCR4 Comple- Reset- Output Synchro- mentary Synchro- Level Master Clear Clock Operating Mode nization FDIR PWM nized PWM Buffering XTGD Select Enable Select Select Synchronous preset SYNC4 = 1 —...
Page 295: Programmable Timing Pattern Controller
Section 9 Programmable Timing Pattern Controller 9.1 Overview The H8/3039 Series has a built-in programmable timing pattern controller (TPC) * that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 296: Block Diagram
9.1.2 Block Diagram Figure 9-1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR NDRA...
Page 297: Tpc Pins
9.1.3 TPC Pins Table 9-1 summarizes the TPC output pins. Table 9-1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 298: Registers
9.1.4 Registers Table 9-2 summarizes the TPC registers. Table 9-2 TPC Registers Address* Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR R/(W)* H'00 H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register...
Page 299: Register Descriptions
9.2 Register Descriptions 9.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 300: Port B Data Direction Register (Pbddr)
9.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7, 5 to 0 These bits select input or...
Page 301: Next Data Register A (Ndra)
9.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 302 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Page 303: Next Data Register B (Ndrb)
9.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP )*. During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 304 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3)* is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Page 305: Next Data Enable Register A (Ndera)
9.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 306: Next Data Enable Register B (Nderb)
9.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP )* on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 307: Tpc Output Control Register (Tpcr)
9.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 308 Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit6 G3CMS1 G3CMS0 Description TPC output group 3 (TP to TP )* is triggered by compare match in ITU channel 0...
Page 309 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit2 G1CMS1 G1CMS0 Description TPC output group 1 (TP to TP ) is triggered by compare match in ITU channel 0...
Page 310: Tpc Output Mode Register (Tpmr)
9.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC to TP ) ∗...
Page 311 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at compare (Initial value) match A in the selected ITU channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Note: * Since this LSI does not have a TP...
Page 312: Operation
9.3 Operation 9.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 313: Output Timing
9.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 9-3 shows the timing of these operations for the case of normal output in groups 0 and 1, triggered by compare match A. ø...
Page 314: Normal Tpc Output
9.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 9-4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited). Set the TPC output trigger period.
Page 315 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRA PADR • The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 316: Non-Overlapping Tpc Output
9.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 9-6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set the TPC output trigger period in GRB Set GR values and the non-overlap margin in GRA.
Page 317 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRA PADR Non-overlap margin • The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
Page 318: Tpc Output Triggering By Input Capture
9.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 319: Usage Notes
9.4 Usage Notes 9.4.1 Operation of TPC Output Pins to TP * are multiplexed with ITU pin functions. When ITU output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 320 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 321: Section 10 Watchdog Timer
Section 10 Watchdog Timer 10.1 Overview The H8/3039 Series has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3039 Series chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten.
Page 322: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources ø/2 RSTCSR ø/32 ø/64 Reset Reset control Clock ø/128 (internal, external) Clock selector ø/256...
Page 323: Register Configuration
10.1.4 Register Configuration Table 10-2 summarizes the WDT registers. Table 10-2 WDT Registers Address* Write* Read Name Abbreviation Initial Value H'FFA8 H'FFA8 Timer control/status register TCSR R/(W)* H'18 H'FFA9 Timer counter TCNT H'00 H'FFAA H'FFAB Reset control/status register RSTCSR R/(W)* H'3F Notes: 1.
Page 324: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Initial value Read/Write When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR.
Page 325: Timer Control/Status Register (Tcsr)
10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 326 Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00 Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer.
Page 327: Reset Control/Status Register (Rstcsr)
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (ø), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description ø/2 (Initial value) ø/32 ø/64...
Page 328 Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin* initialize external system devices.
Page 329: Notes On Register Access
10.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions.
Page 330 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 10-3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 331: Operation
10.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 10.3.1 Watchdog Timer Operation Figure 10-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR.
Page 332: Interval Timer Operation
WDT overflow H'FF TME set to 1 TCNT count value H'00 OVF = 1 Start H'00 written Reset H'00 written in TCNT in TCNT Internal reset signal 518 states RESO 132 states Figure 10-4 Watchdog Timer Operation (Masked ROM Version) 10.3.2 Interval Timer Operation Figure 10-5 illustrates interval timer operation.
Page 333: Timing Of Setting Of Overflow Flag (Ovf)
10.3.3 Timing of Setting of Overflow Flag (OVF) Figure 10-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 334: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 10-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 335: Interrupts
10.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 10.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 336: Section 11 Serial Communication Interface
Section 11 Serial Communication Interface 11.1 Overview The H8/3039 Series has a serial communication interface (SCI) with two independent channels. The two channels are functionally identical. The SCI can communicate in asynchronous or synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 337 • Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • Built-in baud rate generator with selectable bit rates •...
Page 338: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the SCI. Internal data bus Module data bus ø Baud rate ø/4 generator Transmit/ ø/16 receive control ø/64 Parity generation Clock Parity check External clock Legend RSR: Receive shift register RDR: Receive data register TSR:...
Page 339: Input/Output Pins
11.1.3 Input/Output Pins The SCI has the serial pins for each channel as listed in table 11-1. Table 11-1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output Serial clock pin...
Page 340: Register Descriptions
11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) RSR is an 8-bit register that receives serial data. Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 341: Transmit Shift Register (Tsr)
11.2.3 Transmit Shift Register (TSR) TSR is an 8-bit register used to transmit serial data. Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 342: Serial Mode Register (Smr)
11.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator’s clock source Multiprocessor mode...
Page 343 Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 Description Asynchronous mode (Initial value) Synchronous mode Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 Description 8-bit data...
Page 344 Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit. The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode.
Page 345 Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 11.3.3, Multiprocessor Communication Function.
Page 346: Serial Control Register (Scr)
11.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0 These bits select the SCI clock source Transmit end interrupt enable...
Page 347 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value) Transmit-data-empty interrupt request (TXI) is enabled Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then...
Page 348 Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 349 Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0;...
Page 350: Serial Status Register (Ssr)
11.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer Value of multi- processor bit to be transmitted Multiprocessor bit...
Page 351 The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written.
Page 352 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally (Initial value)* [Clearing conditions] The chip is reset or enters standby mode. Software reads ORER while it is set to 1, then writes 0. A receive overrun error occurred* [Setting condition] Reception of the next serial data ends when RDRF = 1.
Page 353 Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0.
Page 354: Bit Rate Register (Brr)
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1 Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its...
Page 355 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode ø (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.16 0.16 0.21 0.16 0.16 0.21 0.16 1200 0.16 –0.70 0.16 2400 0.16 1.14...
Page 356 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16...
Page 357 Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 14.7456 Bit Rate Error Error Error Error (bits/s) –0.17 0.70 0.03 –0.12 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 0.16 2400 0.16 0.16...
Page 358 Table 11-4 Examples of Bit Rates and BRR Settings in Synchronous Mode ø (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k...
Page 359 SMR Settings Clock Source CKS1 CKS0 ø ø/4 ø/16 ø/64 The bit rate error in asynchronous mode is calculated as follows. ø × 10 –1} ×100 Error (%) ={ (N + 1) × B × 64 × 2 2n-1...
Page 360 Table 11-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 11-6 and 11-7 indicate the maximum bit rates with external clock input. Table 11-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings ø (MHz) Maximum Bit Rate (bits/s) 62500 2.097152...
Page 361 Table 11-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 362 Table 11-7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0...
Page 363: Operation
11.3 Operation 11.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 11-8.
Page 364 Table 11-8 SMR Settings and Serial Communication Formats SCI Communication Format SMR Settings Multi- Stop Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity STOP Mode Lengt h Lengt h Asynchronous 8-bit data Absent Absent 1 bit mode 2 bits Pr es ent...
Page 365: Operation In Asynchronous Mode
11.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible.
Page 366 Communication Formats: Table 11-10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 11-10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data...
Page 367 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 11-9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Page 368 Start of initialization Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after Clear TE and RE bits the setting is made in SCR. to 0 in SCR Select the communication format in SMR.
Page 369 Transmitting Serial Data (Asynchronous Mode): Figure 11-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, Start transmitting check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0.
Page 370 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 371 Receiving Serial Data (Asynchronous Mode): Figure 11-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling and break Start receiving detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify...
Page 372 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 11-7 Sample Flowchart for Receiving Serial Data (2)
Page 373 In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 374: Multiprocessor Communication
Figure 11-8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Page 375 Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11-11. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01)
Page 376 Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 11-10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE...
Page 377 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 378 Receiving Multiprocessor Serial Data: Figure 11-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read Set MPIE bit to 1 in SCR...
Page 379 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER flags to 0 in SSR Figure 11-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
Page 380 Figure 11-13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads Not own ID, so No RXI request, (multiprocessor RDR data and clears MPIE bit is set...
Page 381: Synchronous Operation
11.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 382 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 383 Transmitting Serial Data (Synchronous Mode): Figure 11-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit Start transmitting data in TDR and clear the TDRE flag to 0.
Page 384 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 385 Figure 11-17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt handler request writes data in TDR request request and clears TDRE flag to 0...
Page 386 Receiving Serial Data (Synchronous Mode): Figure 11-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 387 Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 11-18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • The SCI synchronizes with serial clock input or output and initializes internally. •...
Page 388 Figure 11-19 shows an example of SCI receive operation. Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt handler request reads data in RDR and request Overrun error, clears RDRF flag to 0...
Page 389 SCI initialization: the transmit data output function of the TxD pin and Initialize receive data input function of the RxD pin are selected, enabling Start transmitting and receiving simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that Read TDRE flag in SSR the TDRE flag is 1, then write transmit data in TDR and clear...
Page 390: Sci Interrupts
11.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11-12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCR.
Page 391: Usage Notes
11.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 392 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 393 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). | D –...
Page 394 TDRE Continuous transmission Note: Make sure that t is at least 5 states. Figure 11-22 Transmission in Synchronous Mode (Example) Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI: 1. Problem in Operation After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is switched to the port function at the end of transmission, a low-level signal is output for one half- cycle before the port output state is established.
Page 395 2. Usage Note The procedure shown below should be used to prevent low-level output when switching from the SCK pin function to the port function. As this procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit.With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 396: Section 12 Smart Card Interface
Section 12 Smart Card Interface 12.1 Overview SCI0 supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.
Page 397: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the Smart Card interface. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check Legend : Smart Card mode register SCMR : Receive shift register : Receive data register...
Page 398: Pin Configuration
12.1.3 Pin Configuration Table 12-1 shows the Smart Card interface pin configuration. Table 12-1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin 0 Output clock output Receive data pin 0 Input receive data input Transmit data pin 0 Output transmit data output 12.1.4...
Page 399: Register Descriptions
12.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 12.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value Read/Write — — — —...
Page 400 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 12.3.4, Register Settings.
Page 401: Serial Status Register (Ssr)
12.2.2 Serial Status Register (SSR) TDRE RDRF MPBT ORER TEND Initial value R/(W) R/(W) R/(W) R/(W) R/(W) Transmit end Status flag indicating end of transmission Error signal status Status flag indicating that an error signal has been received Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode.
Page 402 Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit are as shown below. Bit 2 TEND Description Transmission is in progress [Clearing conditions] (Initial value) •...
Page 403: Operation
12.3 Operation 12.3.1 Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit and plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
Page 404 Data line Clock line Px (port) H8/3039 Series Reset line IC card Chip Connected equipment Figure 12-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
Page 405: Data Format
12.3.3 Data Format Figure 12-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
Page 406 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts a date transfer of one frame. The data frame starts with a start bit (Ds, low-level).
Page 407: Register Settings
12.3.4 Register Settings Table 12-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 12-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
Page 408 SCMR Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
Page 409: Clock
12.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 12-5 shows some sample bit rates.
Page 410 The method of calculating the value from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. ø × 10 – 1 1488 ×...
Page 411: Data Transfer Operations
12.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 412 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 12-4 shows an example of the transmission processing flow, and figure 12-5 shows the relation between a transmit operation and the internal registers.
Page 413 Start Initialization Start transmission ERS=0? Error processing TEND=1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS=0? Error processing TEND=1? Clear TE bit to 0 Figure 12-4 Example of Transmission Processing Flow...
Page 414 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output Data 1 (3) Serial data output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 415 Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 12-6 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Page 416 With the above processing, interrupt servicing is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated.
Page 417: Usage Note
12.4 Usage Note The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate.
Page 418 Thus the reception margin in smart card interface mode is given by the following formula.  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10)
Page 419 Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 12-8 Retransfer Operation in SCI Receive Mode •...
Page 420: Section 13 A/D Converter
Section 13 A/D Converter 13.1 Overview The H8/3039 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 17.6, Module Standby Function.
Page 421: Block Diagram
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – ø/8 Comparator Analog Control circuit multi- plexer Sample-and- ø/16 hold circuit interrupt ADTRG Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA:...
Page 422: Input Pins
13.1.3 Input Pins Table 13-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 423: Register Configuration
13.1.4 Register Configuration Table 13-2 summarizes the A/D converter’s registers. Table 13-2 A/D Converter Registers Address* Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high) ADDRBH H'00 H'FFE3...
Page 424: Register Descriptions
13.2 Register Descriptions 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) — ADDRn — — — — — Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 425: A/D Control/Status Register (Adcsr)
13.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts...
Page 426 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value) Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Page 427 Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 13.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description Single mode (Initial value) Scan mode Bit 3—Clock Select (CKS): Selects the A/D conversion time.
Page 428: A/D Control Register (Adcr)
13.2.3 A/D Control Register (ADCR) TRGE — — — — — — — Initial value Read/Write — — — — — — — Reserved bits Trigger enable Enables or disables external triggering of A/D conversion ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion.
Page 429: Cpu Interface
13.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 430: Operation
13.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 13.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 431 Figure 13-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 432: Scan Mode (Scan = 1)
13.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 433 Figure 13-4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected)
Page 434: Input Sampling And A/D Conversion Time
13.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 13-5 shows the A/D conversion timing.
Page 435: External Trigger Input Timing
Table 13-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 13.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 436: Interrupts
13.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 13.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN...
Page 437 If a filter capacitor is connected as shown in figure 13-7, the input currents at the analog input pins to AN ) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance ), an error will arise in the analog input pin voltage.Therefore careful consideration is required when deciding the circuit constants.
Page 438 Table 13-5 Analog Pin Specifications Item Unit Analog input capacitance — Permissible signal source impedance — kΩ = 4.0 V to 5.5 V and ø ≤ 12 MHz Note: * When V 10 kΩ To A/D converter 20 pF Note: Values are reference values. Figure 13-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8/3039 Series A/D conversion precision definitions are given below.
Page 439 • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 13-9 A/D Conversion Precision Definitions (1)
Page 440 Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 13-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8/3039 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ...
Page 441 Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AV Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, thus acting as antennas.
Page 442: Section 14 Ram
Section 14 RAM 14.1 Overview The H8/3039 has 4 kbytes of on-chip static RAM, H8/3038 has 2 kbytes, H8/3037 has 1 kbyte, and H8/3036 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer.
Page 443: Block Diagram
14.1.1 Block Diagram Figure 14-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Bus interface SYSCR H'FEF10 H'FEF11 H'FEF12* H'FEF13 On-chip RAM H'FFF0E * H'FFF0F * Even addresses Odd addresses Legend SYSCR: System control register...
Page 444: System Control Register (Syscr)
14.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable bit Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 445: Operation
14.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip RAM when addressing the addresses shown in Table 4-1 in each operation mode. When the RAME bit is cleared to 0 in modes 1, 3, and 5 (expanded modes), external address space is accessed.
Page 446: Section 15 Rom
Section 15 ROM 15.1 Overview The H8/3039 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8/3038 has 64 kbytes, the H8/3037 has 32 kbytes and H8/3036 has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
Page 447: Overview Of Flash Memory
15.2 Overview of Flash Memory 15.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase. The block to be erased can be specified by setting the corresponding bit.
Page 448: Block Diagram
• Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. 15.2.2 Block Diagram Figure 15-1 shows a block diagram of the flash memory. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR* EBR*...
Page 449: Pin Configuration
15.2.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 15-2. Table 15-2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable FWE* Input Flash program/erase protection by hardware Mode 2 Input Sets this LSI operating mode Mode 1...
Page 450: Register Descriptions
15.3 Register Descriptions 15.3.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit.
Page 451 Modes 1 Initial value to 4, and 6 Modes 5 Initial value and 7 Program mode Designates transition to or exit from program mode Erase mode Designates transition to or exit from erase mode Program-verify mode Designates transition to or exit from program-verify mode Erase-verify mode Designates transition to...
Page 452 Bit 6: Description Program/erase disabled (Initial value) Program/erase enabled [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU) * : Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5: Description Erase setup cleared...
Page 453 Bit 2: Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1, and SWE = 1 Bit 1—Erase (E) * : Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.
Page 454: Erase Block Register (Ebr)
15.3.2 Erase Block Register (EBR) EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to H'00 by a reset, in hardware standby mode, or software standby mode, when a high level is not input to the FWE terminal, or when the FLMCR SWE bit is 0 when a high level is applied to the FWE terminal.
Page 455: Ram Control Register (Ramcr)
Table 15-4 Flash Memory Erase Blocks Block (Size) Address EB0 (1 kbyte) H'00000 to H'003FF EB1 (1 kbyte) H'00400 to H'007FF EB2 (1 kbyte) H'00800 to H'00BFF EB3 (1 kbyte) H'00C00 to H'00FFF EB4 (28 kbytes) H'01000 to H'07FFF EB5 (32 kbytes) H'08000 to H'0FFFF EB6 (32 kbytes) H'10000 to H'17FFF...
Page 456 Bit 3—RAM Select (RAMS): Is used with bits 2 to 1 to reassign an area to RAM (see table 15-5). The initial setting for this bit is 0 in Modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled. It is initialized by a reset and in hardware standby mode.
Page 457: Flash Memory Status Register (Flmsr)
15.3.4 Flash Memory Status Register (FLMSR) The flash memory status register (FLMSR) detects flash memory errors. FLER — — — — — — — Initial value — — — — — — — Reserved bits Flash memory error Status flag indicating that an error was detected during programming or erasing Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was...
Page 458: On-Board Programming Modes
15.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 15-6.
Page 459: Boot Mode
On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to this chip (originally incorporated in the chip) is the case where the old program version or data started, an SCI communication check is carried...
Page 460 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the When the FWE pin is driven high, user software programming/ erase control program to on-chip confirms this fact, executes the transfer program RAM should be written into the flash memory by in the flash memory, and transfers the the user beforehand.
Page 461 15.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. In reset start, after setting this LSI pin to the boot mode, start the microcomputer boot program, measure the Low period of the data sent from the host, and select the bit rate register (BRR) value beforehand.
Page 462 Start Set pins to boot program mode Set this LSI to the boot mode and reset starts the LSI. and execute reset-start Set the host to the prescribed bit rate (4800, 9600) Host transfers data (H'00) and consecutively send H'00 data in 8-bit data, continuously at prescribed bit rate 1 stop bit format.
Page 463 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 15-7 Measuring the low period of the communication data from the host When boot mode is initiated, this LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host (figure 15-7).
Page 464 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 15-8. The boot program area can be used when a transition is made to the execution state for the user program transferred to RAM.
Page 465 (5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing the RE and TE bits in serial control register (SCR)) before branching to the user program. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD is in the high level output state (P9DDR P9 DDR=1, P9DR P9 DR=1).
Page 466: User Program Mode
15.4.2 User Program Mode When set to the user program mode, this LSI can erase and program its flash memory by executing a user program. Therefore, on-chip flash memory on-board programming can be performed by providing a means of controlling FWE and supplying the write data on the board and providing a write program in a part of the program area.
Page 467 <Procedure> The user writes a program that executes steps 3 to 8 in advance - MD =101, 111 as shown below . Sets the mode pin to an on-chip ROM enable mode (mode 5 or 7). Reset start Starts the CPU via reset. (The CPU can also be started from the user program mode by setting the FWE pin to High level during reset;...
Page 468: Programming/Erasing Flash Memory
15.5 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR.
Page 469: Program Mode
Erase setup state Erase mode Normal mode FWE=1 FWE=0 Erase-verify mode On-board SWE=1 Software programming mode reprogramming software reprogramming enable state disable state SWE=0 Program setup state Programming mode Program-verify mode Notes: : Normal mode : On-board programming mode 1. Do not make a state transition by setting or clearing two or more bits at the same time.
Page 470: Program-Verify Mode
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register (FLMCR), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. (The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0.) 32 consecutive byte data transfers are performed.
Page 471 Start Set SWE bit in FLMCR Wait (x) µsec Store 32-byte write data in write data area and reprogram data area Programming operation counter n ← 1 Notes: 1. Programming should be performed in the erased state. Consecutively write 32-byte data in (Perform 32-byte programming on memory after all 32 bytes reprogram data area in RAM to flash memory have been erased.)
Page 472: Erase Mode
15.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 15-12. For the wait time (x, y, z, α, β, γ, ε, η) after setting or clearing of each bit in the flash memory control register (FLMCR) and the maximum erase count (N), see table 18-15 of section 18.2.5, Flash Memory Characteristics.
Page 473 Start Set SWE bit in FLMCR Wait (x) µsec Erase counter n ← 1 Set EBR Enable WDT Set ESU bit in FLMCR Wait (y) µsec Set E bit in FLMCR Start of erase Wait (z) msec Clear E bit in FLMCR End of erase Wait (α) µsec Clear ESU bit in FLMCR...
Page 474: Flash Memory Protection
15.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 15.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in the flash memory control register (FLMCR) and erase block register (EBR).
Page 475 Table 15-8 Hardware Protection Function Item Description Program Erase Verify* FWE pin protection • When a low level is input to the FWE pin, FLMCR and EBR are initialized, and the program/erase-protected state is entered.* • Reset/standby In a reset (including a WDT overflow protection reset) and in standby mode, FLMCR and EBR are initialized, and the...
Page 476: Software Protection
15.6.2 Software Protection Software protection can be implemented by setting the RAMS bit in RAM control register (RAMCR) and erase block register (EBR). When software protection is in effect, setting the P or E bit in flash memory control register (FLMCR) does not cause a transition to program mode or erase mode.
Page 477 Figure 15-13 shows the flash memory state transition diagram. Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is disabled. For more information, see section 15.6.4, NMI Input Disable Conditions. 2.
Page 478: Nmi Input Disable Conditions
Therefore, to prevent such erroneous operation, operation must be carried out correctly in according with the program/erase algorithms in the state that flash write enable (FWE) is set. In addition, the operation must be always carried out correctly by supervising microcomputer errors inside and outside the chip with the watchdog timer, etc.
Page 479: Flash Memory Emulation By Ram
b. If a value has not yet been written to the NMI vector table, NMI exception handling will not be performed correctly. 15.7 Flash Memory Emulation by RAM Erasing and programming the flash memory takes time, which can make it difficult to tune parameters and other data in real time.
Page 480: Flash Memory Prom Mode
This LSI has a PROM mode, besides an on-board programming mode, as a flash memory program/erase mode. In the PROM mode, a program can be freely written to the on-chip ROM using a PROM programmer that supports the Hitachi 128kbytes flash memory on-chip microcomputer device type.
Page 481: Prom Mode Operation
15.8.3 PROM Mode Operation Table 15-10 shows how the different operating modes are set when using PROM mode, and table 15-11 lists the commands used in PROM mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 482 Table 15-11 PROM Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write H'71 Write...
Page 483 15.8.4 Memory Read Mode AC Characteristics Table 15-13 AC Characteristics in Memory Read Mode Transition = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle — nxtc CE hold time —...
Page 484 Table 15-14 AC Characteristics in Memory Contents Read = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Access time — CE output delay time — OE output delay time — Output disable delay time —...
Page 485 Table 15-15 AC Characteristics in Transition from Memory Read Mode to Another Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle — nxtc CE hold time —...
Page 486 15.8.5 Auto-Program Mode AC Characteristics Table 15-16 AC Characteristics in Auto-Program Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle — nxtc CE hold time — CE setup time —...
Page 487 ADDRESS STABLE A16-0 nxtc nxtc wsts Data transfer 1byte to 128bytes write I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'00 H'40 I/O5-0 Figure 15-20 Auto-Program Mode Timing Waveforms Cautions on Use of Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers.
Page 488 15.8.6 Auto-Erase Mode AC Characteristics Table 15-17 AC Characteristics in Auto-Erase Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle — nxtc CE hold time — CE setup time —...
Page 489 A16-0 nxtc nxtc ests erase I/O7 Erase end identification signal I/O6 Erase normal and confirmation signal H'00 H'20 H'20 I/O5-0 Figure 15-21 Auto-Erase Mode Timing Waveforms Caution on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. •...
Page 490 15.8.7 Status Read Mode AC Characteristics Table 15-18 AC Characteristics in Status Read Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle — nxtc CE hold time —...
Page 491: Prom Mode Transition Time
Table 15-19 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address identifica- erase error count tion exceeded Initial value Indications Normal Command...
Page 492: Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 493: Notes On Flash Memory Programming/Erasing
(1) Program/erase with the specified voltage and timing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM writer that supports the Hitachi 128kbytes flash memory on-board microcomputer device type. Do not set the PROM writer at the HN28F101. If the PROM writer is set to the HN28F101 by mistake, a high level can be input to the FWE pin and the LSI can be destroyed.
Page 494 • In the boot mode, perform FWE pin High/Low switching during reset. In transition to the boot mode, input FWE=High level and set MD to MD while the RES input is low. At this time, the FWE and MD to MD inputs must satisfy the mode programming setup time (t ) relative to the reset clear timing.
Page 495 (8) Do not perform additional programming. Reprogram flash memory after erasing. With on-board programming, program to 32-byte programming unit blocks one time only. Program to 128-byte programming unit blocks one time only even in the PROM mode. Erase all the programming unit blocks before reprogramming. Bus release must also be disabled.
Page 496 Programming and erase possible Wait time: x φ min 0µs OSC1 to MD clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1.
Page 497 Programming Programming Programming and Wait Programming and Wait erase erase time: x time: x Wait time: x erase possible Wait time: x possible erase possible possible φ OSC1 min 0µs to MD RESW SWE set SWE clear SWE bit User Boot mode Mode switching * Mode...
Page 498: Mask Rom Overview
15.10 Mask ROM Overview 15.10.1 Block Diagram Figure 15-28 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'00000 H'00001 H'00002 H'00003 On-chip ROM H'1FFFE H'1FFFF Even addresses Odd addresses Figure 15-28 ROM Block Diagram (H8/3039)
Page 499: Notes On Ordering Mask Rom Version Chip
15.11 Notes on Ordering Mask ROM Version Chip When ordering the H8/3039 Series chips with a mask ROM, note the following. • When ordering through an EPROM, use a 128-kbyte one. • Fill all the unused addresses with H'FF as shown in figure15-29 to make the ROM data size 128 kbytes for all H8/3039 Series chips, which incorporate different sizes of ROM.
Page 500: Section 16 Clock Pulse Generator
Section 16 Clock Pulse Generator 16.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other internal clock signals (ø/2 to ø/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (ø). The system clock is output at the ø pin* and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules.
Page 501: Block Diagram
16.1.1 Block Diagram Figure 16-1 shows a block diagram of the clock pulse generator. XTAL Duty Frequency adjustment Oscillator Prescalers divider circuit EXTAL Division control register ø ø/2 to ø/4096 Data bus Figure 16-1 Block Diagram of Clock Pulse Generator...
Page 502: Oscillator Circuit
16.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 16.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 16-2. The damping resistance Rd should be selected according to table 16-1.
Page 503 Table 16-2 Crystal Resonator Parameters (Preliminary) Frequency (MHz) 2 Rs max (Ω) Co (pF) 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max Use a crystal resonator with a frequency equal to the system clock frequency (ø). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from...
Page 504: External Clock Input
16.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 16-5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. EXTAL External clock input XTAL...
Page 505 External Clock: The external clock frequency should be equal to the system clock frequency (ø). Table 16-3 and figure 16-6 indicate the clock timing. Table 16-3 Clock Timing 5.0 V ±10% 2.7 V to 5.5 V Item Symbol Unit Test Conditions External clock —...
Page 506 Table 16-4 and Figure 16-7 show the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t ).
Page 507: Duty Adjustment Circuit
16.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø). 16.4 Prescalers The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096). 16.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (ø).
Page 508: Division Control Register (Divcr)
16.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. — — — — — — DIV1 DIV0 Initial value Read/Write — — — — — — Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio DIVCR is initialized to H'FC by a reset and in hardware standby mode.
Page 509: Section 17 Power-Down State
Section 17 Power-Down State 17.1 Overview This LSI has a power-down state that greatly reduces power consumption by halting CPU functions, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 510 Table 17-1 Power-Down State and Module Standby Function State Entering Supporting φclock Exiting Modules output Ports Mode Conditions Clock Registers SCI0 SCI1 Methods φoutput Sleep SLEEP instruc- Active Halted Held Active Active Active Active Active Held Held • Interrupt mode tion executed •...
Page 511: Register Configuration
17.2 Register Configuration This LSI has a system control register (SYSCR) that controls the power-down state, and a module standby control register (MSTCR) that controls the module standby function. Table 17-2 summarizes this register. Table 17-2 Register Configuration Address* Name Abbreviation Initial Value H’FFF2...
Page 512 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description SLEEP instruction causes transition to sleep mode...
Page 513: Module Standby Control Register (Mstcr)
17.2.2 Module Standby Control Register (MSTCR) MSTCR is an 8-bit readable/writable register that controls output of the system clock (ø). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter modules.
Page 514 Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby. Bit 4 MSTOP4 Description SCI0 operates normally (Initial value) SCI0 is in standby state Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby. Bit 3 MSTOP3 Description SCI1 operates normally...
Page 515: Sleep Mode
17.3 Sleep Mode 17.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 516: Software Standby Mode
17.4 Software Standby Mode 17.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 517: Selection Of Oscillator Waiting Time After Exit From Software Standby Mode
17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR, and its DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, and DIV1 and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 518: Sample Application Of Software Standby Mode
17.4.4 Sample Application of Software Standby Mode Figure 17-1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 519: Transition To Hardware Standby Mode
17.5 Hardware Standby Mode 17.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained.
Page 520: Module Standby Function
17.6 Module Standby Function 17.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0, SCI1, and A/D converter) independently of the power-down state. This standby function is controlled by bits MSTOP5 to MSTOP3 and MSTOP0 in MSTCR. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle.
Page 521: System Clock Output Disabling Function
17.7 System Clock Output Disabling Function Output of the system clock (ø) can be controlled by the PSTOP bit in MSTCR. When the PSTOP bit is set to 1, output of the system clock halts and the ø pin is placed in the high-impedance state. Figure 17-3 shows the timing of the stopping and starting of system clock output.
Page 522: Section 18 Electrical Characteristics
Section 18 Electrical Characteristics 18.1 Electrical characteristics of Masked ROM Version 18.1.1 Absolute Maximum Ratings Table 18-1 lists the absolute maximum ratings. Table 18-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 7)* –0.3 to V +0.3 Input voltage (port 7)
Page 523: Dc Characteristics
18.1.2 DC Characteristics Table 18-2 lists the DC characteristics. Table 18-3 lists the permissible output currents. Table 18-2 DC Characteristics (1) = 5.0 V ± 10%, AV = 5.0 V ± 10%,V Conditions: = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item...
Page 524 Table 18-2 DC Characteristics (1) (cont) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Typ Max Unit Test Conditions...
Page 525 Table 18-2 DC Characteristics (1) (cont) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test C ondi t i ons NMI, RES Input...
Page 526 Table 18-2 DC Characteristics (2) Conditions: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions ×...
Page 527 Table 18-2 DC Characteristics (2) (cont) Conditions: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 528 Table 18-2 DC Characteristics (2) (cont) Conditions: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions NMI, RES...
Page 529 Table 18-2 DC Characteristics (3) Conditions: = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 530 Table 18-2 DC Characteristics (3) (cont) Conditions: = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 531 Table 18-2 DC Characteristics (3) (cont) Conditions: = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 532 Table 18-3 Permissible Output Currents Conditions: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Permissible output...
Page 533 2 kΩ Port Darlington pair Figure 18-1 Darlington Pair Drive Circuit (Example) Ports 600Ω Figure 18-2 LED Drive Circuit (Example)
Page 534: Ac Characteristics
18.1.3 AC Characteristics Bus timing parameters are listed in table 18-4. Control signal timing parameters are listed in table 18-5. Timing parameters of the on-chip supporting modules are listed in table 18-6. Table 18-4 Bus Timing Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø...
Page 535 Table 18-4 Bus Timing (cont) Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) Condition B:...
Page 536 Table 18-5 Control Signal Timing Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) Condition B:...
Page 537 Table 18-6 Timing of On-Chip Supporting Modules Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) Condition B:...
Page 538 Table 18-6 Timing of On-Chip Supporting Modules (cont) Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) Condition B:...
Page 539 C = 90 pF: ports 1, 2, 3, 5, 6, 8, ø C = 30 pF: ports 9, A, B This LSI output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels • Low: 0.8 V •...
Page 540: A/D Conversion Characteristics
18.1.4 A/D Conversion Characteristics Table 18-7 lists the A/D conversion characteristics. Table 18-7 A/D Converter Characteristics Condition A: = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, ø = 2 MHz to 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-...
Page 541: Electrical Characteristics Of Flash Memory Version
18.2 Electrical characteristics of Flash Memory Version 18.2.1 Absolute Maximum Ratings Table 18-8 lists the absolute maximum ratings. Table 18-8 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 7)* –0.3 to V +0.3 Input voltage (port 7) –0.3 to AV...
Page 542: Dc Characteristics
18.2.2 DC Characteristics Table 18-9 lists the DC characteristics. Table 18-10 lists the permissible output currents. Table 18-9 DC Characteristics (1) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 543 Table 18-9 DC Characteristics (1) (cont) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = AV = 0 V*, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) (Programming/Erasing Conditions: T = 0°C to +75°C (regular specifications), = 0°C to +85°C (wide-range specifications)) Item...
Page 544 Table 18-9 DC Characteristics (1) (cont) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) (Programming/Erasing Conditions: T = 0°C to +75°C (regular specifications), = 0°C to +85°C (wide-range specifications)) Item...
Page 545 Table 18-9 DC Characteristics (2) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) (Programming/Erasing Conditions: V = 3.0 V to 3.6 V, T = 0°C to +75°C (regular specifications), T...
Page 546 Table 18-9 DC Characteristics (2) (cont) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) (Programming/Erasing Conditions: V = 3.0 V to 3.6 V, T = 0°C to +75°C...
Page 547 Table 18-10 Permissible Output Currents Conditions: = 3.0 V to 5.5V, AV = 3.0 V to 5.5V, V = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Permissible output low Ports 1, 2, 5 and B —...
Page 548 2 kΩ Port Darlington pair Figure 18-4 Darlington Pair Drive Circuit (Example) Ports 600Ω Figure 18-5 LED Drive Circuit (Example)
Page 549: Ac Characteristics
18.2.3 AC Characteristics Bus timing parameters are listed in table 18-11. Control signal timing parameters are listed in table 18-12. Timing parameters of the on-chip supporting modules are listed in table 18-13. Table 18-11 Bus Timing Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø...
Page 550 Table 18-11 Bus Timing (cont) Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø = 2 to 10 MHz, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) = 5.0 V ±...
Page 551 Table 18-12 Control Signal Timing Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø = 2 to 10 MHz, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) = 5.0 V ±...
Page 552 Table 18-13 Timing of On-Chip Supporting Modules Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø = 2 to 10 MHz, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) = 5.0 V ±...
Page 553 Table 18-13 Timing of On-Chip Supporting Modules (cont) Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø = 2 to 10 MHz, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) = 5.0 V ±...
Page 554 C = 90 pF: ports 1, 2, 3, 5, 6, 8, ø This LSI C = 30 pF: ports 9, A, B output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels • Low: 0.8 V •...
Page 555: A/D Conversion Characteristics
18.2.4 A/D Conversion Characteristics Table 18-14 lists the A/D conversion characteristics. Table 18-14 A/D Converter Characteristics Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, ø = 2 to 10 MHz, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 556: Flash Memory Characteristics
18.2.5 Flash Memory Characteristics Table 18-15 shows the flash memory characteristics. Table 18-15 Flash Memory Characteristics (1) Conditions: =4.5 V to 5.5V, AV =4.5 V to 5.5V, V = 0°C to +75°C (program/erase operating temperature range: regular specifications), T = 0°C to +85°C (program/erase operating temperature range: wide-range specifications) Test Item...
Page 557 Table 18-15 Flash Memory Characteristics (2) Conditions: =3.0 V to 3.6 V, AV =3.0 V to 3.6V, V =0°C to +75°C (Programming/erasing operating temperature range: regular specification) T =0°C to +85°C (Programming/erasing operating temperature range: wide-range specification) Test Item Symbol Unit Condition Programming time*...
Page 558: Operational Timing
18.3 Operational Timing This section shows timing diagrams. 18.3.1 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 18-7 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 18-8 shows the timing of the external three-state access cycle.
Page 559 ø to A ACC3 ACC3 (read) ACC1 to D (read) WR (write) WSW1 WDS1 to D (write) Figure 18-7 Basic Bus Cycle: Two-State Access...
Page 560 ø to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 WR (write) WDS2 to D (write) Figure 18-8 Basic Bus Cycle: Three-State Access...
Page 561 ø to A RD (read) to D (read) WR (write) to D (write) WAIT Figure 18-9 Basic Bus Cycle: Three-State Access with One Wait State...
Page 562: Control Signal Timing
18.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 18-10 shows the reset input timing. • Reset output timing Figure 18-11 shows the reset output timing. • Interrupt input timing Figure 18-12 shows the interrupt input timing for NMI and IRQ , IRQ , IRQ , and IRQ...
Page 563 ø NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0, 1, 4, and 5) NMIW (j = 0, 1) Figure 18-12 Interrupt Input Timing...
Page 564: Clock Timing
18.3.3 Clock Timing Clock timing is shown below. • Oscillator settling timing Figure 18-13 shows the oscillator settling timing. ø STBY OSC1 OSC1 Figure 18-13 Oscillator Settling Timing 18.3.4 TPC and I/O Port Timing TPC and I/O port timing is shown below. ø...
Page 565: Itu Timing
18.3.5 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 18-15 shows the ITU input/output timing. • ITU external clock input timing Figure 18-16 shows the ITU external clock input timing. ø TOCD Output compare TICS Input capture Notes: 1.
Page 566: Sci Input/Output Timing
18.3.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 18-17 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 18-18 shows the SCI input/output timing in synchronous mode. SCKr SCKf SCKW Scyc...
Page 567: Appendix A Instruction Set
Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Description General destination register* General source register* General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 568 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 569 Table A-1 Instruction Set Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd — — 0 — @ERs →...
Page 570 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — W Rs16 → @ERd MOV.W Rs, @ERd — — 0 —...
Page 571 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W SP–2 → SP 2 — — ◊ ◊ PUSH.W Rn 0 — Rn16 → @SP SP–4 → SP 4 —...
Page 572 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust —...
Page 573 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z W ERd32 ÷ Rs16 →ERd32 DIVXU. W Rs, ERd — — (6) (7) — — (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 574 Table A-1 Instruction Set (cont) Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — 0 —...
Page 575 Table A-1 Instruction Set (cont) Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd —...
Page 576 Table A-1 Instruction Set (cont) Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 577 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 —...
Page 578 Table A-1 Instruction Set (cont) Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) —...
Page 579 Table A-1 Instruction Set (cont) Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z Z ∨ (N ⊕ V) BLE d:8 — If condition — — — — — — is true then BLE d:16 —...
Page 580 Table A-1 Instruction Set (cont) System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — PC → @–SP TRAPA #x:2 1 — — — — — CCR → @–SP <vector> → PC —...
Page 581 Table A-1 Instruction Set (cont) Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation H N Z — if R4L ≠ 0 then 8+4n *2 EEPMOV. B 4 — — — — — — repeat @R5 →...
Page 582: Operation Code Maps
A.2 Operation Code Maps Table A-2 Operetion Code Map (1) Instruction code: 1st byte 2nd byte Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. Table A.2 Table A.2 Table A.2 Table A.2 XORC ANDC...
Page 583 Table A-2 Operation Code Map (2) 1st byte 2nd byte Instruction code: AH AL Table A.2 Table A.2 Table A.2 LDC/STC SLEEP ADDS ADDS SHLL SHAL SHLL SHAL SHLR SHLR SHAR SHAR ROTXL ROTL ROTXL ROTL ROTXR ROTR ROTXR ROTR EXTU EXTU EXTS...
Page 584 Table A-2 Operation Code Map (3) 3rd byte 1st byte 2nd byte 4th byte Instruction code: Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. ALBH BLCH 01406 01C05 MULXS MULXS 01D05 DIVXS DIVXS...
Page 585: Number Of States Required For Execution
A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A-3 indicates the number of states required per cycle according to the bus size. Table A-4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction.
Page 586 Table A-3 Number of States per Cycle Access Conditions On-Chip Sup- External Device porting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 2 3 + m Branch address read Stack operation Byte data access...
Page 587 Table A-4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 588 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 589 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd...
Page 590 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Wo rd Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd...
Page 591 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR...
Page 592 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), MOV.L @(d:24, ERs), MOV.L @ERs+, ERd MOV.L @aa:16, ERd...
Page 593 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack B yt e Data W ord Data Internal Fetch Addr. Read Operation A ccess A ccess Operation Instruction Mnemonic ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd...
Page 594 Table A-4 Number of Cycles per Instruction (cont) Instruction Branch Stack B yt e Data W ord Data Internal Fetch Addr. Read Operation A ccess A ccess Operation Instruction Mnemonic STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @–ERd STC CCR, @aa:16...
Page 595: Appendix B Internal I/O Register Field
Appendix B Internal I/O Register Field B.1 Addresses Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'1C H'1D H'1E H'1F H'20 — —...
Page 596 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'3B — — — — — — — — — H'3C — — — —...
Page 597 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'60 TSTR — — — STR4 STR3 STR2 STR1 STR0 H'61 TSNC — — —...
Page 598 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'82 TCR3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU channel 3 H'83 TIOR3 —...
Page 599 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'A0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV H'A1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 H'A2 NDERB NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9...
Page 600 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'B8 STOP CKS1 CKS0 SCI1 H'B9 — — — — — — — — H'BA MPIE TEIE...
Page 601 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'D8 P2PCR PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Port 2 H'D9...
Page 602 Data Address Register Bit Names (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'F0 — — — — — — — — — H'F1 MDCR — — —...
Page 603: Function
B.2 Function Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values Initial value Names of the Read/Write —...
Page 604 FLMCR—Flash Memory Control Register H'40 Flash memory Modes 1 to Initial value 4, and 6 Read/Write Modes 5 Initial value Read/Write and 7 Program mode Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase mode Erase mode cleared (Initial value) Transition to erase mode...
Page 605 EBR—Erase Block Register H'42 Flash memory Modes 1 to Initial value 4, and 6 Read/Write Modes 5 Initial value to 7 Read/Write Block 7 to 0 Block EB7 to EB0 is not selected (Initial value) Block EB7 to EB0 is selected Note: When not erasing flash memory, EBR should be cleared to H'00.
Page 606 RAMCR—RAM Control Register H'47 Flash Memory — — — — RAMS RAM2 RAM1 — Modes Initial value 1 to 4 — — — — — Modes Initial value 5 to 7 — — — — R/W* R/W* R/W* — Reserved bits RAM select, RAM2, RAM1 Bit 3 Bit 2...
Page 607 FLMSR—Flash Memory Status Register H'4D Flash memory FLER — — — — — — — Initial value Read/Write — — — — — — — Flash memory error Flash memory write/erase protection is disabled (Initial value) An error has occurred during flash memory writing/erasing Flash memory error protection is enabled DIVCR—Division Control Register H'5D...
Page 608 MSTCR—Module Standby Control Register H'5E System control PSTOP — MSTOP5 MSTOP4 MSTOP3 — — MSTOP0 Initial value Read/Write — Module standby 0 0 A/D converter operates normally 1 A/D converter is in standby state Module standby 3 0 SCI1 operates normally 1 SCI1 is in standby state Module standby 4 0 SCI0 operates normally...
Page 609 TSTR—Timer Start Register H'60 ITU (all channels) — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — — Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting...
Page 610 TSNC—Timer Synchro Register H'61 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized...
Page 611 TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally...
Page 612 TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally...
Page 613 TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input...
Page 614 TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 GRA Function GRA is an output No output at compare match compare register 0 output at GRA compare match...
Page 615 TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled 1 IMIB interrupt requested by IMFB is enabled...
Page 616 TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] TCNT = GRA when GRA functions as a compare match register.
Page 617 TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value Read/Write Output compare or input capture register TCR1—Timer Control Register 1 H'6E...
Page 618 TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 — — — — —...
Page 619 GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 620 TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Notes: 1. Bit functions are the same as for ITU0. Channel 2 does not have a compare match toggle output function. If this setting is used, 1 output will be selected automatically.
Page 621 TIER2—Timer Interrupt Enable Register 2 H'7A ITU2 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Note: Bit functions are the same as for ITU0. TSR2—Timer Status Register 2 H'7B ITU2 — — —...
Page 622 GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR3—Timer Control Register 3 H'82 ITU3...
Page 623 TIER3—Timer Interrupt Enable Register 3 H'84 ITU3 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Note: Bit functions are the same as for ITU0. TSR3—Timer Status Register 3 H'85 ITU3 — — —...
Page 624 GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3...
Page 625 TOER—Timer Output Enable Register H'90 ITU (all channels) — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings...
Page 626 TOCR—Timer Output Control Register H'91 ITU (all channels) — — — XTGD — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted 1 TIOCA , TIOCA , and TIOCB outputs are not inverted...
Page 627 TCR4—Timer Control Register 4 H'92 ITU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value...
Page 628 TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4...
Page 629 BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Group 0 non-overlap 0 Normal TPC output in group 0 Output values change at compare match A in the selected ITU channel...
Page 630 TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 0 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 1 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 2 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 3...
Page 631 NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description TPC outputs TP to TP * are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP * are enabled (NDR15 to NDR8 are transferred to PB to PB )
Page 632 NDRB—Next Data Register B H'A4/H'A6 • Same output trigger for TPC output groups 2 and 3 Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Next output data for Next output data for TPC output group 3* TPC output group 2 Address H'FFA6 —...
Page 633 NDRA—Next Data Register A H'A5/H'A7 • Same output trigger for TPC output groups 0 and 1 Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Next output data for Next output data for TPC output group 1 TPC output group 0 Address H'FFA7 —...
Page 634 TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Timer enable Clock select 2 to 0 TCNT is initialized to H'00 and halted CKS2 CKS1 CKS0 Description ø/2 TCNT is counting ø/32 Timer mode select ø/64 0 Interval timer: requests interval timer interrupts ø/128...
Page 635 TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — — — Reset output enable 0 Reset signal is not output externally 1 Reset signal is output externally Watchdog timer reset 0 [Clearing condition]...
Page 636 SMR—Serial Mode Register H'B0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source ø clock Multiprocessor mode ø/4 clock 0 Multiprocessor function disabled ø/16 clock 1 Multiprocessor format selected ø/64 clock Stop bit length 0 One stop bit...
Page 637 BRR—Bit Rate Register H'B1 SCI0 Initial value Read/Write Serial communication bit rate setting...
Page 638 SCR—Serial Control Register H'B2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 2 CKE1 CKE2 Clock Selection and Output Asynchronous mode Internal clock, SCK pin available for generic input/output Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output Synchronous mode...
Page 639 TDR—Transmit Data Register H'B3 SCI0 Initial value Read/Write Serial transmit data...
Page 640 SSR—Serial Status Register H'B4 SCI0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in receive data is 1 transmit data is 1...
Page 641 RDR—Receive Data Register H'B5 SCI0 Initial value Read/Write Serial receive data SCMR—Smart Card Mode Register H'B6 SCI0 — — — — SDIR SINV — SMIF Initial value Read/Write — — — — — Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 Unmodified TDR contents are transmitted...
Page 642 SMR—Serial Mode Register H'B8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'B9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'BA SCI1 MPIE...
Page 643 RDR—Receive Data Register H'BD SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. P1DDR—Port 1 Data Direction Register H'C0 Port 1 P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Initial value Modes 1 and 3...
Page 644 P1DR—Port 1 Data Register H'C2 Port 1 Initial value Read/Write Data for port 1 pins P2DR—Port 2 Data Register H'C3 Port 2 Initial value Read/Write Data for port 2 pins P3DDR—Port 3 Data Direction Register H'C4 Port 3 P3 DDR P3 DDR P3 DDR P3 DDR...
Page 645 P3DR—Port 3 Data Register H'C6 Port 3 Initial value Read/Write Data for port 3 pins P5DDR—Port 5 Data Direction Register H'C8 Port 5 — — — — P5 DDR P5 DDR P5 DDR P5 DDR Initial value Modes 1 and 3 Read/Write —...
Page 646 P6DDR—Port 6 Data Direction Register H'C9 Port 6 — — P6 DDR P6 DDR P6 DDR — — P6 DDR Initial value Read/Write — Port 6 input/output select 0 Generic input 1 Generic output P5DR—Port 5 Data Register H'CA Port 5 —...
Page 647 P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — — — — P8 DDR P8 DDR Initial value Read/Write — — — Port 8 input/output select 0 Generic input 1 Generic output P7DR—Port 7 Data Register H'CE Port 7 Initial value —...
Page 648 P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — P9 DDR P9 DDR P9 DDR Initial value Read/Write — — Port 9 input/output select 0 Generic input 1 Generic output PADDR—Port A Data Direction Register H'D1 Port A PA DDR PA DDR PA DDR PA DDR...
Page 649 PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B input/output select 0 Generic input...
Page 650 P2PCR—Port 2 Input Pull-Up Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
Page 651 ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — — — — Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 — — — —...
Page 652 ADCR—A/D Control Register H'E9 TRGE — — — — — — — Initial value Read/Write — — — — — — — Trigger enable 0 A/D conversion cannot be externally triggered 1 A/D conversion starts at the fall of the external trigger signal ( ADTRG...
Page 653 ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection Description Single Mode Scan Mode Scan mode AN , AN 0 Single mode...
Page 654 ASTCR—Access State Control Register H'ED Bus controller AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 Number of States in Access Cycle Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas WCR—Wait Control Register H'EE...
Page 655 WCER—Wait Controller Enable Register H'EF Bus controller WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0 Initial value Read/Write Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled MDCR—Mode Control Register H'F1 System control —...
Page 656 SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 657 ADRCR—Address Control Register H'F3 Bus controller — — — — — Modes Initial value 1 and Read/Write — — — — — — — 5 to 7 Initial value Mode 3 Read/Write — — — — Address 23 to 21 enable 0 Address output 1 I/O pins other than the above...
Page 658 ISCR—IRQ Sense Control Register H'F4 Interrupt controller — — IRQ5SC IRQ4SC — — IRQ1SC IRQ0SC Initial value Read/Write IRQ , IRQ , IRQ and IRQ sense control 0 Interrupts are requested when IRQ , IRQ , IRQ , and IRQ inputs are low 1 Interrupts are requested by falling-edge input at IRQ , IRQ , IRQ and IRQ...
Page 659 ISR—IRQ Status Register H'F6 Interrupt controller — — IRQ5F IRQ4F — — IRQ1F IRQ0F Initial value Read/Write — — R/(W)* R/(W) * — — R/(W) * R/(W) * , IRQ , IRQ and IRQ flags Bits 5, 4, 1 and 0 IRQ5F IRQ4F IRQ1F...
Page 660 IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 — IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7, A6, A4 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 661: Appendix C I/O Block Diagrams
Appendix C I/O Block Diagrams C.1 Port 1 Block Diagram Software standby Modes 6 and 7 Hardware standby Modes 1, 3, and 5 Reset WP1D Modes 6 and 7 Reset Modes 1, 3, and 5 WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1...
Page 662: Port 2 Block Diagram
C.2 Port 2 Block Diagram Reset Modes Software standby RP2P 6 and 7 WP2P Hardware standby Reset Modes 1, 3, and 5 WP2D Modes 6 and 7 Reset Modes 1, 3, and 5 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2:...
Page 663: Port 3 Block Diagram
C.3 Port 3 Block Diagram Reset Hardware Modes 6 and 7 standby Write to external address WP3D Reset Modes 6 and 7 Modes 1, 3, and 5 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7 Figure C-3 Port 3 Block Diagram...
Page 664: Port 5 Block Diagram
C.4 Port 5 Block Diagram Reset Software standby Modes RP5P 6 and 7 Hardware standby WP5P Modes 1, 3 Reset WP5D Modes 6 and 7 Reset Modes 1, 3, and 5 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D: Write to P5DDR WP5: Write to port 5 RP5:...
Page 665: Port 6 Block Diagram
C.5 Port 6 Block Diagram Reset Bus controller Modes 6 and 7 WP6D WAIT Reset input enable Bus controller WAIT output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-5 (a) Port 6 Block Diagram (Pin P6...
Page 666 Software standby Modes 6 and 7 Hardware standby Reset WP6D Reset Modes 6 and 7 Modes 1, 3, and 5 AS output RD output WR output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 3 to 5 Figure C-5 (b) Port 6 Block Diagram (Pins P6 to P6...
Page 667: Port 7 Block Diagram
C.6 Port 7 Block Diagram A/D converter Input enable Analog input RP7: Read port 7 n = 0 to 7 Figure C-6 Port 7 Block Diagram...
Page 668: Port 8 Block Diagram
C.7 Port 8 Block Diagram Reset WP8D Reset Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-7(a) Port 8 Block Diagram (Pin P8...
Page 669 Reset WP8D Reset Modes 6 and 7 Modes 1, 3, and 5 Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-7 (b) Port 8 Block Diagram (Pin P8...
Page 670: Port 9 Block Diagram
C.8 Port 9 Block Diagram Reset WP9D Reset SCI0 Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (a) Port 9 Block Diagram (Pin P9...
Page 671 Reset WP9D Reset SCI1 Output enable Serial transmit data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C-8 (b) Port 9 Block Diagram (Pin P9...
Page 672 Reset WP9D Input enable Reset Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 2, 3 Figure C-8 (c) Port 9 Block Diagram (Pin P9 , P9...
Page 673 Reset WP9D Clock input enable Reset Clock output enable Clock output Clock input WP9D: Write to P9DDR WP9: Write to port 9 Interrupt controller RP9: Read port 9 4 and 5 input Figure C-8 (d) Port 9 Block Diagram (Pin P9 , P9...
Page 674: Port A Block Diagram
C.9 Port A Block Diagram Reset WPAD Reset TPC output enable Next data Output trigger Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 or 1 Figure C-9 (a) Port A Block Diagram (Pins PA , PA...
Page 675 Reset WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input Counter input clock WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2 or 3 Figure C-9 (b) Port A Block Diagram (Pins PA , PA...
Page 676 Software standby Address output enable Mode 3 Reset WPAD TPC output Reset enable Next data Output trigger Output enable Compare match output Input capture input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 4 to 7 Note: PA address output enable is fixed at 1 in mode 3.
Page 677: Port B Block Diagram
C.10 Port B Block Diagram Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 3 Figure C-10 (a) Port B Block Diagram (Pins PB to PB...
Page 678 Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 4 or 5 Figure C-10 (b) Port B Block Diagram (Pins PB , PB...
Page 679 Reset WPBD Reset TPC output enable Next data Output trigger A/D converter ADTRG input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C-10 (c) Port B Block Diagram (Pin PB...
Page 680: Appendix Dpin States
Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Hardware Software Program Standby Standby Execution State Pin Name Mode Reset State Mode Mode Sleep Mode ø — Clock output T Clock output RESO* RESO — to P1 1, 3 to A...
Page 681 Table D-1 Port States (cont) Hardware Software Program Standby Standby Execution State Pin Name Mode Reset State Mode Mode Sleep Mode to P7 1, 3, 5 to 7 Input port 1, 3, 5 keep I/O port 6, 7 keep I/O port 1, 3, 5 T [DDR = 0] Input port [DDR = 0]...
Page 682: Pin States At Reset
D.2 Pin States at Reset Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 683 Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
Page 684 Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus outputs are held during the T state.The same timing applies when a reset occurs in the state of an access cycle to a two-state-access area.
Page 685: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
Page 686: Appendix F Product Code Lineup
Appendix F Product Code Lineup Table F-1 H8/3039 Series Product Code Lineup Package (Hitachi Package Product Type Product Code Mark Code Code) H8/3039 Flash memory HD64F3039F HD64F3039F 80-pin QFP (FP-80A) version version HD64F3039TE HD64F3039TE 80-pin TQFP (TFP-80C) HD64F3039VF HD64F3039VF 80-pin QFP (FP-80A)
Page 687: Appendix G Package Dimensions
Appendix G Package Dimensions Figures G-1 and G-2 show the H8/3039 Series FP-80A and TFP-80C package dimensions. 17.2 ± 0.3 Unit: mm *0.32 ± 0.08 0.12 M 0.30 ± 0.06 0.83 0° – 8° 0.8 ± 0.3 0.10 *Dimension including the plating thickness Base material dimension Figure G-1 Package Dimensions (FP-80A)
Page 688 14.0 ± 0.2 Unit: mm *0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 *Dimension including the plating thickness Base material dimension Figure G-2 Package Dimensions (TFP-80C)
Page 689 Publication Date: 1st Edition, December 1997 2nd Edition, December 1998 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

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Hitachi F-ZTAT H8/3039 Series Hardware Manual

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