Nand Flash Operation - Sharp LH79524 User Manual

Boot Controller

3.1.1.1 NAND Flash Operation

When NAND Flash is detected as the boot code source, the Boot Controller forces an over-
ride of nCS1. Instead, the Boot ROM is selected for the locations in the memory map
where nCS1 is normally selected and the Boot Rom code is executed. The Boot ROM code
manages the interface to the NAND Flash device. The nCS1 override can be disabled by
writing a 0 to the nCS1 Override Control bit in the CS1OV register.
The Boot Controller generates the control signals on the nFRE and nFWE pins for external
NAND Flash. nFRE is the active LOW signal to the NAND flash Read Enable pin. This sig-
nal is the External Memory Controller's nOE, enabled by the signal on external address pin
A23. Note that the LH79524/LH79525 memory controller automatically indexes address
signals on the address pins, depending on the width of the memory devices. For example,
with 8-bit addressing, the A0 signal is presented on pin A0, and the A23 signal is presented
on pin A23. For 16-bit memory, the memory controller automatically shifts the address one
bit to the right so that all addresses fall on half-word boundaries. In this configuration, sig-
nal A1 is presented on pin A0, and pin A23 carries the A24 signal. Similarly, for 32-bit
devices, A2 appears on pin A0, and A25 appears on pin A23. For more information on
booting from NAND Flash, refer to Section 7.3.1 and Section 7.3.2.
nFRE is only active (i.e., LOW) when nOE is LOW and the A23 signal (for 8-bit), A24 signal
(for 16-bit), or A25 (for 32-bit) is HIGH. nFWE is the active LOW signal to the NAND flash
Write Enable pin. This signal is the External Memory Controller's nWE signal, enabled by
address signal A23/A24/A25. nFWE is only active (i.e., LOW) when nWE is LOW and
A23/A24/A25 is HIGH. Gating these signals allows normal memory and I/O accesses to
other external devices to occur during extended NAND Flash accesses (when chip select
is held active). These other devices must be mapped to external memory regions where
the address signals are LOW.
3.1.2 Hardware Design Considerations
Using the Boot Controller dictates certain hardware considerations, especially when boot-
ing from NAND Flash.
3.1.2.1 Active Pullups To Signal Boot Mode
The boot mode — NOR Flash, NAND Flash, SRAM, I
value latched on the rising edge of the nRESETIN signal from the state of PC[7:4],
shown in Table 3-1 and Table 3-2. PC[7:6] are used during NAND Flash booting as control
signals, but PC[5:4] have no other use following the end of reset. Therefore, those two
GPIO pins can be used during normal operation if an active pullup is used, gated by the
nRESETOUT signal.
Figure 3-2 shows a schematic representation of one active pullup circuit. One circuit is
required for each PCx pin to be pulled high during reset. nRESETOUT is presented to the
Gate (pin 1) of the P-Channel FET. When active (LOW), nRESETout causes the transistor
to turn on, and pull the PCx input HIGH. When nRESETOUT transitions from LOW to HIGH
at the end of the reset period, the value on PC[7:4] is latched and the FET is turned off, thus
allowing those pins to be used for general purpose I/O or as address pins A[21:20].
3-4 Version 1.0
LH79524/LH79525 User's Guide
2
C, or UART — is selected by the