Table 4-24. Intren Register; Table 4-25. Intren Fields; Interrupt Enable Register (Intren) - Sharp LH79524 User Manual

Color Liquid Crystal Display Controller

4.5.3.6 Interrupt Enable Register (INTREN)

INTREN is the Interrupt Enable Register. Setting bits within this register enables the
corresponding Raw Interrupt Status bit values to be passed to the Raw Interrupt Status
Register (see Section 4.5.3.8).
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
4-28

Table 4-24. INTREN Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 4-25. INTREN Fields

BIT NAME
Reserved Reading returns 0. Write the reset value.
31:5 ///
Bus Master Error Interrupt Enable
1 = Interrupt enabled
4 MBEIEN
0 = Interrupt disabled
Vertical Compare Interrupt Enable
3 VCIEN 1 = Interrupt enabled
0 = Interrupt disabled
Next Base Update Interrupt Enable
2 BUIEN 1 = Interrupt enabled
0 = Interrupt disabled
FIFO Underflow Interrupt Enable
1 FUIEN 1 = Interrupt enabled
0 = Interrupt disabled
0 /// Reserved Reading returns 0. Write the reset value.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF4000 + 0x18
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
///
0 0
RO RO