Table 6-20. Instatus Register; Table 6-21. Instatus Fields; Interrupt Status Register (Instatus) - Sharp LH79524 User Manual

Ethernet MAC Controller

6.3.2.8 Interrupt Status Register (INSTATUS)

The EMAC generates a single interrupt. This register indicates the source of this interrupt.
For test purposes each bit can be set or reset by directly writing to the interrupt status reg-
ister regardless of the state of the mask register. Otherwise the corresponding bit in the
MASK register must be cleared for a bit to be set. All bits are reset to zero on read. If any
bit is set in this register, the Ethernet Interrupt signal will be asserted
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:14
13
12
11
10
9
8
6-30

Table 6-20. INSTATUS Register

31 30 29 28 27
0
RO
15 14 13 12 11
///
0 0 0 0
RO RW RW RW

Table 6-21. INSTATUS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Pause Time Zero Indicates the PAUSETIME register has decre-
mented to zero. This bit is reset to 0 when read.
PAUSEZERO
1 = PAUSETIME decremented to zero
0 = PAUSETIME not decremented to zero
Pause Frame Received Indicates a valid Pause Frame has been
received. This bit is reset to 0 when read.
PAUSEFRRX
1 = Valid pause frame received
0 = No valid pause frame received
Response Not OK Indicates that the DMA Block receives response
'Not OK'. This bit is reset to 0 when read.
NOTOK
1 = Response 'Not OK'
0 = Normal operation
Receive Overrun The DMA Block was unable to store the receive
frame to memory.
RECOVERRUN
1 = Receive overrun
0 = No overrun
Reserved Reading returns 0. Write the reset value.
///
/// Reserved Reading returns 0. Write the reset value.
26 25 24 23
///
10 9 8 7
0 0 0 0
RW RW RO RW
0xFFFC7000 + 0x24
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
.
22 21 20 19 18
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
1 0
0 0
RW RW