Table 10-9. Ris Register; Table 10-10. Ris Register Definitions; Raw Interrupt Status Register (Ris) - Sharp LH79524 User Manual

2
I S Converter

10.2.2.4 Raw Interrupt Status Register (RIS)

This register provides the current raw status value of the corresponding interrupt prior to
masking. Writing has no effect. For each bit, 1 = TRUE and 0 = FALSE.
The SSPPERIS, ECPERIS and TXUERIS interrupts are set as soon as the given error
conditions are met (a rising edge on the error detection logic). Once cleared by a write to
the appropriate ICR bit, the interrupt bit will not be set again until a new error has been
detected (the next rising edge on the error detection logic). This prevents the interrupt from
being immediately re-set for the same error. The condition causing the error must be
resolved and asserted again to trigger a new interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6
5
4
3
2
1
0
10-18
31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO

Table 10-10. RIS Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
SSP Protocol Error raw interrupt status Indicates that the SSP is
SSPPERIS configured for a data size other than 16 bits. Applies only to I
Applies to both Slave and Master Mode operation.
External Codec Protocol Error raw interrupt status Indicates that the
ECPERIS external CODEC (the source of the frame input in slave mode) is configured
for a data size other than 16 bits. Applies only to slave mode I
Transmit Underrun Error raw interrupt status Transmission has
TXUERIS begun while the transmit FIFO is empty. Applies to SSP and slave mode
2
I S transactions.
Transmit FIFO raw interrupt status (from SSP RIS:TXRIS bit) Gives the
TXRIS
raw interrupt state (prior to masking) of the Transmit FIFO interrupt.
Receive FIFO raw interrupt status (from SSP RIS:RXRIS bit) Gives the
RXRIS
raw interrupt state (prior to masking) of the Receive FIFO interrupt.
Receive timeout raw interrupt status (from SSP RIS:RTRIS bit) Gives
RTRIS
the raw interrupt state (prior to masking) of the Receive Timeout interrupt
Receive overrun raw interrupt status (from SSP RIS:RORRIS bit) Gives
RORRIS
the raw interrupt state (prior to masking) of the Receive Overrun interrupt

Table 10-9. RIS Register

27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC8000 + 0x00C
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 0
RO RO RO RO RO
2
S transactions.
2
S transactions.
17 16
0 0
RO RO
1 0
0 0
RO RO