Table 13-14. Rststatusclr Register; Table 13-15. Rststatusclr Fields; Reset Status Clear Register (Rststatusclr) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR)

This Write Only register clears the two Reset Status flags in the RSTSTATUS register.
Writing 1 to this register causes the corresponding bit in the RSTSTATUS to be cleared to
0. Writing 0 has no effect on the corresponding bit in the Reset Status register. Writing to
reserved bits has no effect on the RCPC.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:2
1
0
13-16

Table 13-14. RSTSTATUSCLR Register

31 30 29 28 27
— — — —
WO WO WO WO WO
15 14 13 12 11
— — — —
WO WO WO WO WO

Table 13-15. RSTSTATUSCLR Fields

NAME
/// Reserved Reads undefined. Write 0 only.
Clear WDT Timeout Write 1 to clear the WDTO status bit. Reads return
unpredictable results.
TOCLR
1 = Clears WDTO bit in the RSTSTATUS Register to 0
0 = No effect
Clear External Reset Write 1 to clear the EXT status bit. Reads return
unpredictable results.
EXTCLR
1 = Clears EXT bit in the RSTSTATUS Register to 0
0 = No effect
26 25 24 23
///
— — — — —
WO WO WO WO
10 9 8 7
///
— — — — —
WO WO WO WO
0xFFFE2000 + 0x14
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
— — — — —
WO WO WO WO WO
6 5 4 3 2
— — — — —
WO WO WO WO WO
17 16
— —
WO WO
1 0
— —
WO WO