Table 7-4. 16-Bit Address Mapping; General Nand Flash Access - Sharp LH79524 User Manual

External Memory Controller

7.3.2 General NAND Flash Access

At all other times but boot, all address lines function as addresses, and the NAND
Flash control signals must be generated by the application software. Unlike booting, where
the internal boot code automatically translates the addresses as required by the data
width, in general application use, the software must perform this translation prior to writing
to the NAND Flash.
7.3.2.1 Transaction Example
This example uses the design in Figure 7-14, with the four address lines connected to
ALE, CLE, nWE, and nRE on the NAND Flash. The design can, obviously, use any
address lines or GPIO to control the device.
Since NAND Flash devices are available in several widths, it is up to software to ensure
that the proper control signals appear on the proper address pins for correct operation
(Recall from Section 7.2.2.1.3 that the SoC right justifies addressing).
For example, using pins D[15:0] to communicate with the NAND Flash requires program-
ming SCONFIGx:MW to 0b01 for 16-bit wide external memory transactions. This also
causes the automatic address shift to place the A1 address signal on pin A0. Thus, if the
design uses a 16-bit NAND Flash, software must assure TRUE conditions on the address
signals for the operation being executed, as shown in Table 7-4. A 16-bit addressing
example appears in Section 7.3.2.3.
7-20

Table 7-4. 16-bit Address Mapping

SIGNAL
A3 A2 (ALE)
A4 A3 (CLE)
A23 PC6/A22/nFWE
A24 PC7/A23/nFRE
Version 1.0
LH79524/LH79525 User's Guide
OUTPUT PIN