Table 7-47. Dyncfgx Register; Table 7-48. Dyncfgx Fields; Dynamic Configuration Register For Ndcs0 And Ndcs1 (Dyncfgx) - Sharp LH79524 User Manual

External Memory Controller
7.5.2.19 Dynamic Configuration Register for nDCS0
and nDCS1 (DYNCFGx)
The Dynamic Configuration Register specifies the configuration information for the rele-
vant dynamic memory Chip Select. These registers are normally only modified during sys-
tem initialization.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:21
20
19
18:15
14
13
12:7
6:5
4:3
2:0
7-48

Table 7-47. DYNCFGx Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// AM ///
0 0 0 0 0
RW RW RW RW RW

Table 7-48. DYNCFGx Fields

/// Reserved Reading returns 0. Write the reset value.
Write Protect
P
1 = Write protected
0 = Not Write protected
Read and Write Buffer Enable The Buffer Enable bit must be set to 1 for prop-
er SDRAM interface operation. The buffers must be disabled during SDRAM and
SyncFlash initialization. They must also be disabled when performing SyncFlash
commands. The buffers must be enabled during normal operation.
B NOTE: The buffers must be disabled during SDRAM and SyncFlash initializa-
tion, and when performing SyncFlash commands. The buffers must be enabled
during normal operation.
1 = Read and Write Buffers enabled for accesses to this Chip Select
0 = Read and Write Buffers disabled for accesses to this Chip Select
/// Reserved Read undefined, must write as zeros.
AM Address Mapping See Table 7-49
/// Reserved Read undefined, must write as zeros.
AM Address Mapping See Table 7-49
/// Reserved Read undefined, must write as zeros.
Memory Device
00 = SDRAM
MD
01 = low-power SDRAM
10 = Micron SyncFlash
11 = reserved
/// Reserved Read undefined, must write as zeros.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
AM
0 0 0 0
RW RW RW RW
0xFFFF1000 + 0x100 for DYNCFG0
0xFFFF1000 + 0x120 for DYNCFG1
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
B
0 0 0 0 0
RO RO RW RW RW
6 5 4 3 2
/// MD
0 0 0 0 0
RW RW RW RW RW
17 16
///
0 0
RW RW
1 0
///
0 0
RW RW