Sharp LH79524 User Manual page 464

Chapter 16
UARTs
The LH79524/LH79525 contains three UARTs, UART[2:0]. The UARTs feature:
• Character Length: Programmable number of data bits per character (5, 6, 7, or 8). Even,
odd, stick, or no-parity bit generation and detection. 1 or 2 Stop bit generation.
• Optional Nine-bit Mode to tag and recognize characters as either data or address
• FIFOs: The transmit FIFO is 9 bits wide and the receive FIFO is 12 bits wide. Each has pro-
grammable service 'trigger levels' (empty/full, 1/8, 1/4, 1/2, 3/4, and 7/8) and overrun pro-
tection. The receive FIFO is 12 bits wide to accommodate 8 bits of data and receive flags
(framing, parity/9th bit, break error, or overrun) that are placed in the receive FIFO. The
transmit FIFO is 9 bits wide to accommodate 8 data bits plus the optional Nine-bit Mode
tag. The transmit and receive FIFOs can be disabled to act like a one-byte holding register.
Both FIFOs are 32 entries deep.
• Programmable baud rate generator: This enables division of the UART input clock by 16
to 65535 × 16 and generates an internal clock that is common to both transmit and
receive portions of the UART. The divisor can be a fractional number.
• Interrupts: The UART can issue an interrupt on transmit and receive FIFO watermarks,
on errors, on a received address in Nine-bit Mode, and on receiver timeout. Each inter-
rupt can be individually enabled and masked.
• DMA: Support for Direct Memory Access (DMA); UART0 only.
• Line break: Generate and detect breaks using UART transactions.
• Loopback testing: Programmed by writing the appropriate values to the control registers.
Data transmitted on UARTTXD will then be received on the UARTRXD input.
• Independent Clocks: UART clock operates asynchronously to the system clock.
• IrDA support
• RTS and CTS modem control lines on UART0
Figure 16-1 shows a block diagram of UART0, UART1, and UART2.
Version 1.0 16-1