Table 5-2. Dma Memory Map; Table 5-3. Dma Data Stream Register Summary (One Set Of Registers For Each Of The Four Data Streams In Table 5-2) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
5.2 Register Reference
This section provides the DMA Controller register memory mapping and bit fields.
5.2.1 Memory Map
Each stream has the identical set of 11 registers. The base address for each stream is
shown in Table 5-2. The 11 registers are summarized in Table 5-3. The address offset
listed is with reference to the particular stream's base address, shown in Table 5-2. For
example, the address for the DESTLO register for STREAM2 is:
(STREAM2 Base = 0xFFFE1080) + (DESTLO Offset = 0x008) = 0xFFFE1088
DATASTREAM
STREAM0
STREAM1
STREAM2
STREAM3
MASK
CLR
STATUS
ADDRESS
OFFSET FROM
STREAM BASE
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x2C - 0x3C

Table 5-2. DMA Memory Map

BASE ADDRESS
0xFFFE1000
0xFFFE1040
0xFFFE1080
0xFFFE10C0
0xFFFE10F0
0xFFFE10F4
0xFFFE10F8
Table 5-3. DMA Data Stream Register Summary
(One Set of Registers for Each of the Four Data Streams in Table 5-2)
NAME
SOURCELO
SOURCEHI
DESTLO
DESTHI
MAX
CTRL
CURSHI
CURSLO
CURDHI
CURDLO
TCNT
///
Data Stream 0 Register Base Address
Data Stream 1 Register Base Address
Data Stream 2 Register Base Address
Data Stream 3 Register Base Address
DMA Interrupt Mask Register
DMA Interrupt Clear
DMA Status Register
Source Base Address Register, lower 16 bits
Source Base Address Register, higher 16 bits
Destination Base Address Register, lower 16 bits
Destination Base Address Register, higher 16 bits
Maximum Count Register
Control Register
Current Source Address Register, higher 16 bits
Current Source Address Register, lower 16 bits
Current Destination Address Register, higher 16 bits
Current Destination Address Register, lower 16 bits
Terminal Count
Reserved — Do not access
Version 1.0
Direct Memory Access Controller
.
DESCRIPTION
DESCRIPTION
5-5