Figure 15-4. Capture Signal Synchronization Timing; Capture Signal Sampling - Sharp LH79524 User Manual

Timers

15.1.2 Capture Signal Sampling

The capture signal causes the value of the timer to be captured and stored in the Timer
Capture Register (TxCAPn) associated with the particular input pin being used. For exam-
ple, to sample Timer 0 using a trigger on the CTC0A pin, that count would be stored in the
T0CAPA register. Triggers occur on the rising edge of HCLK. The pulse width of a capture
signal must be equal to or longer than, two HCLK periods plus the setup time for the signal
to be correctly read in. After sampling, the external capture signal is synchronized to the ris-
ing edge of HCLK. This synchronization process takes two HCLK periods. After the external
capture signal is synchronized, the value of the counter is stored in the appropriate TxCAPn
Registers. The external capture signal triggering is edge-selectable and can use a rising or
falling edge to capture the counter value.
EXTERNAL
CAPTURE SIGNAL
CAPTURE SIGNAL
AFTER SAMPLING
15.1.3 PWM Mode
Any of the timers may be configured to implement a Pulse Width Modulator (PWM). In
PWM mode, the signal is output on the CTCMPxA pin.
This mode uses a timer's two Timer Compare Registers (TxCMPn) to program the PWM
period and duty cycle. TxCMP1 programs the PWM period, and TxCMP0 programs the
PWM duty cycle. The period must always be larger than the duty cycle. Figure 15-5 illus-
trates this more clearly.
• The value in TxCMP1 Register + 1 is the period of the PWM.
• The value in TxCMP0 Register + 1 is the duty cycle of the PWM.
The PWM is clocked by the internal count clock, which is the prescaled HCLK.
To enable PWM Mode for a Timer, program the CTRLx:PWM bit to 1. With PWM Mode
enabled, program the CTRLx:TC bit to 1. The TC bit causes the Timer Counter Register
(CNTx) to reset to 0x0000 after its count value matches the value of the Timer Compare
Register0 (TxCMP0).
The PWM output on the CTCMPxA pin can be programmed to active HIGH or active LOW
polarity using the CTRLx:CMP[1:0] fields (see the CTRLx register description, and the
example, for programming specifics).
In PWM Mode, PWM CTCMPxB remains LOW or HIGH, depending on the value pro-
grammed into the CTRLx:CMP0 field.
15-4
SYSTEM
CLOCK
EDGE
RISING
SELECTION

Figure 15-4. Capture Signal Synchronization Timing

Version 1.0
LH79524/LH79525 User's Guide
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