Table 15-18. Ctrl1 Register; Table 15-19. Ctrl1 Register Definitions; Timer 1 Control Register (Ctrl1) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

15.2.2.8 Timer 1 Control Register (CTRL1)

This register allows programming various functions, including PWM Mode, clock selection,
and starting/stopping Timer 1.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:15
14
13
12:11 CMP1

Table 15-18. CTRL1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// PWM TC CMP1
0 0 0 0 0
R RW RW RW RW

Table 15-19. CTRL1 Register Definitions

/// Reserved Reading this field returns 0. Write the reset value.
PWM Output This bit allows the use of CTCMP1A as a PWM output. This is
done by programming this bit as well as other bits in this register. Refer to
Section 15.1.3 for a complete explanation and an example.
PWM
0 = Output CTCMP1A is normal and works only with the T0CMP1 Register.
1 = Output CTCMP1A is in PWM Mode.
Timer 1 Operation This bit determines whether Timer 1 counter is to operate
as either a free running counter or as an interval timer. When 1, the counter
clears upon matching CMP1 for Timer 1. This operation is only available with the
TC
CMP1 Register for Timer 1. Refer to Section 15.1.1 for a complete explanation.
0 = Inhibit counter clear (operates as free running counter).
1 = Clear counter when CNT1 for Timer 1 matches T1CMP1 for Timer 1.
Output Value Select Timer/Counter Operation: Programs the value (when a
compare match occurs) output on the CTCMP1B pin when the CNT1 Register
matches T1CMP1.
00 = No change occurs to CTCMP1B
01 = Output 0 to CTCMP1B
10 = Output 1 to CTCMP1B
11 = Toggle the output to CTCMP1B
PWM Operation:
00 = Invalid
01 = Active HIGH PWM output polarity
10 = Active LOW PWM output polarity
11 = Invalid
IMPORTANT: CMP1 and CMP0 must be programmed to the same polarity.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
CMP0 CAPB
0 0 0 0
RW RW RW RW
0xFFFC4000 + 0x30
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
CAPA SEL
0 0 0 0 0
RW RW RW RW RW
Timers
17 16
0 0
RO RO
1 0
CS CCL
0 0
RW RW
15-15