Table 3-5. Supported Devices - Sharp LH79524 User Manual

Boot Controller
3.1.2.2.1 NAND Flash Chip Select
Because of the hardware implementation of the NAND Flash signalling, the LH79524/
LH79525 chip select used for NAND Flash addressing must be nCS0 for booting; nCS1
cannot be used. Connect the nCS0 pin to the NAND Flash nCE input pin if that device is
used for booting. If the NAND Flash is not used for booting, it can be located in any chip
select domain.
3.1.3 Booting Using the I
Booting can also be done using the I
address that must be used is 0b1010000x. This address is not alterable. The Boot Con-
troller will always boot exactly 4Kbytes when using the I2C serial EEPROM.
Interface parameters are shown in Table 3-4 and the list of supported devices is shown
in Table 3-5.
Communication Speed
Mode of SoC
Addressing Mode
2
I C EEPROM Configuration
3-6
2
C Interface
Table 3-4. Boot Parameters for I
PARAMETER

Table 3-5. Supported Devices

DENSITY
32Kbit (4K × 8)
64Kbit (8K × 8)
128Kbit (16K × 8)
256Kbit (32K × 8)
512Kbit (64K × 8)
1Mbit (128K × 8)
2
C interface. When booting from I
400 kHz
Master Mode
7 bit
Slave, addressed at 0b1010000x, where x=0 for Writes and
x=1 for Reads
ATMEL ST MICRO
AT24C32 M24C32
AT24C32 M24C64
AT24C32 M24128
AT24C32 M24256
AT24C32 M24512
AT24C32
Version 1.0
LH79524/LH79525 User's Guide
2
C, the device
2
C
VALUE
MICROCHIP
24xx32
24xx64
24xx128
24xx256
24xx512
N/A N/A