Table 19-4. Rst Description; Table 19-5. Rst Field; Counter Reset Register (Rst) - Sharp LH79524 User Manual

Watchdog Timer

19.2.2.2 Counter Reset Register (RST)

Write this register to reset the WDT, preventing a timeout.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BIT
31:16
15:0
19-6

Table 19-4. RST Description

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
WO WO WO WO WO
NAME
/// Reserved Reading this field returns 0. Write the reset value.
Reset Write 0x1984 to this register to reset the WDT and commence counting
RST
down. If the first timeout interrupt is asserted, this write deasserts the interrupt.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
RST
undefined
WO WO WO WO
0xFFFE3000 + 0x04

Table 19-5. RST Field

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
WO WO WO WO WO
17 16
0 0
RO RO
1 0
WO WO