Table 14-13. Imsc Register; Table 14-14. Imsc Fields; Interrupt Mask Set And Clear Register (Imsc) - Sharp LH79524 User Manual

Synchronous Serial Port

14.2.2.6 Interrupt Mask Set and Clear Register (IMSC)

IMSC is the Interrupt Mask Set and Clear Register. On a read, this register gives the cur-
rent value of the mask on the relevant interrupt. A write of 1 to the particular bit clears the
mask, enabling the interrupt to be read. A write of 0 sets the corresponding mask.
All bits are cleared to 0 when reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
14-16

Table 14-13. IMSC Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
BITS NAME
31:4 /// Reserved Reading returns 0. Write the reset value.
Transmit FIFO Interrupt Mask
3 TXIM
1 = Interrupt not masked
0 = Interrupt is masked
Receive FIFO Interrupt Mask
2 RXIM
1 = Interrupt not masked
0 = Interrupt is masked
Receive Timeout Interrupt Mask
1 RTIM
1 = Interrupt not masked
0 = Interrupt is masked
Receive Overrun Interrupt Mask
0 RORIM
1 = Interrupt not masked
0 = Interrupt is masked
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC6000 + 0x014

Table 14-14. IMSC Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW