Table 17-28. Csr0 Register; Table 17-29. Csr0 Fields; Control Status Register For Ep 0 (Csr0) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

17.2.3.3 Control Status Register for EP 0 (CSR0)

CSR0 provides control and status bits for Endpoint 0.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7
6
5
4
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Clear SETUP_END Bit Software programs a 1 to this bit to clear
SETUP_END (bit 4).
CLR_SETUP_END
1 = Clear the SETUP_END bit to 0
0 = No effect
Clear OUT_PKT_RDY Bit Software programs a 1 to this bit to
clear OUT_PKT_RDY (bit 1).
CLR_OUT
1 = Clear the OUTPACKETRDY bit to 0
0 = No effect
Send STALL Handshake Software writes a 1 to this bit at the same
time it programs a 0 to OUT_PKT_RDY(bit 0) when it decodes an in-
valid token. The USB Host issues a STALL handshake to the current
SEND_STALL
control transfer. Software must write a 0 to end the STALL condition.
1 = Issue STALL Handshake
0 = End STALL condition
Setup Ends This is a Read Only bit. Software programs this bit to
1 when a control transfer ends, before DATA_END (bit 3) is set. Soft-
ware programs this bit to 0, by writing a 1 to the CLR_SETUP_END
(bit 7) bit. When the USB Host programs this bit to 1, an interrupt is
generated to the CPU. When such a condition occurs, the USB Host
SETUP_END
flushes the FIFO, and invalidates CPU access to the FIFO. When
CPU access to the FIFO is invalidated, this bit is programmed to 0.
1 = Control transfer ended
0 = No control transfer end

Table 17-28. CSR0 Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFF5000 + 0x044
(with the INDEX register set to 0)

Table 17-29. CSR0 Fields

Version 1.0
Universal Serial Bus Device
22 21 20 19
0 0 0 0
RO RO RO RO
6 5 4 3
0 0 0 0
RW RW RO RW
FUNCTION
18 17 16
0 0 0
RO RO RO
2 1 0
0 0 0
RW RW RO
17-21