Table 7-13. Status Register; Table 7-14. Status Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.5.2.2 Status Register (STATUS)
The STATUS Register provides memory controller status information.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:3
2
1
0

Table 7-13. STATUS Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Self-refresh Acknowledge This bit indicates the operating mode of the EMC.
SA
1 = Self-refresh Mode
0 = Normal Mode
Write Buffer Status This enables the EMC to enter low-power mode or dis-
abled mode cleanly by determining if the write buffers contain data or not.
WRBUF
1 = Write Buffers contain data
0 = Write Buffers empty
Busy This read-only bit is used to ensure that they memory controller enters
the low-power or disabled mode cleanly by determining if the memory controller
is busy or not.
BUSY
1 = EMC is busy performing memory transactions, commands, auto-refresh
cycles, or is in self-refresh mode.
0 = EMC is idle
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x004

Table 7-14. STATUS Fields

FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
SA
0 0 0 0 1
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 1
RO RO
7-31