Figure 15-2. Count Clock Timing (Hclk In Phase With Ctclk); Figure 15-3. Count Clock Timing (Hclk Not In Phase With Ctclk); Counter Clear Upon Compare Match - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
Figure 15-2 shows the timing of CTCLK with respect to HCLK when the two are in phase.
Figure 15-3 shows the timing of CTCLK with respect to HCLK when the two are not in phase.
SYSTEM
CLOCK
CTCLK
COUNTER
VALUE
SYSTEM
CLOCK
CTCLK
COUNTER
VALUE

15.1.1 Counter Clear Upon Compare Match

A compare match occurs when the contents of the Timer Counter Register (CNTx)
matches the value of the corresponding Timer Compare Register. When there is a com-
pare match, one of two actions occurs, based on the state of the CNTx:TC.
• If TC is programmed to 0, the counter is not cleared and continues counting.
• If TC is programmed to 1, the counter is cleared on the rising edge of the internal
count clock.
When using CMPx as a rising or falling edge trigger ('01' or '10' Output Value Select), the
software must manually clear the compare output. The CMPx hardware provides a highly
accurate edge interrupt.
This output is not automatically set to the opposing value; that is controlled through the pro-
gramming of the output value select bits within the CMP_CAP_CTRL register when the
interrupt is cleared. In this usage mode, the host can clear the output compare signal by
programming the inverse value of the output select bits, set the compare register to 0x01,
enable the counter, and wait for the interrupt. This interrupt will signify that the compare
output is at the original opposing reference level. At this point the counter is ready to be
used for another edge trigger interrupt.
N

Figure 15-2. Count Clock Timing (HCLK in Phase with CTCLK)

N

Figure 15-3. Count Clock Timing (HCLK not in Phase with CTCLK)

N+1
N+1
Version 1.0
Timers
N+2
LH79525-32
N+2
LH79525-33
15-3