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LH79524/LH79525 User's Guide
ADDRESS
OFFSET
0x70
0x74
0x78
0x7C
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
Table 11-1. IOCON Register Summary
NAME
MUXCTL15 Muxing Control 15 For Pin nBLE0/PM4
RESCTL15 Resistor Control 15 Assignment for pin nBLE0/PM4
///
Reserved Do not access
///
Reserved Do not access
///
Reserved Do not access
RESCTL17 Resistor Control 17 Assignment for pin SDCLK
///
Reserved Do not access
///
Reserved Do not access
MUXCTL19 Muxing Control 19 For pins From PE7/nWAIT/nDEOT to PL5/D29
RESCTL19 Resistor Control 19 Assignment for pins from PE7/nWAIT/nDEOT to PL5/D29
MUXCTL20 Muxing Control 20 For pins from PE2/LCDPS to PF6/LCDEN/LCDSPL
Resistor Control 20 Assignment for pins from PE2/LCDPS to
RESCTL20
PF6/LCDEN/LCDSPL
MUXCTL21 Muxing Control 21 For pins from PF5/LCDVD11 to PF2/LCDVD8
RESCTL21 Resistor Control 21 Assignment for pins from PF5/LCDVD11 to PF2/LCDVD8
MUXCTL22 Muxing Control 22 For pins from PF1/LCDVD7 to PG2/LCDVD0
RESCTL22 Resistor Control 22 Assignment for pins from PF1/LCDVD7 to PG2/LCDVD0
MUXCTL23 Muxing Control 23 For pins from PG1/ETHERTXCLK to PH2/ETHERRXCLK
Resistor Control 23 Assignment for pins from PG1/ETHERTXCLK to
RESCTL23
PH2/ETHERRXCLK
MUXCTL24 Muxing Control 24 For pins from PH1/ETHERRXDV to PI3/ETHERCRS
Resistor Control 24 Assignment for pins from PH1/ETHERRXDV to
RESCTL24
PI3/ETHERCRS
MUXCTL25 Muxing Control 25 For pins from AN6/PJ7/INT7 to AN3/LR/Y-/PJ0
///
Reserved Do not access
Version 1.0
I/O Configuration
DESCRIPTION
11-3
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