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LH79524/LH79525 User's Guide
Color Liquid Crystal Display Controller
Table 4-17. TIMING1 Fields (Cont'd)
BIT
NAME
DESCRIPTION
Lines Per Panel
LPP specifies the number of active lines (rows of pixels) per panel. The
LPP bit field is a 10-bit value allowing between 1 and 1,024 lines.
LPP = (Active Lines) – 1
Dual-Panel displays: The two panels in dual-panel displays are assumed to be of identical
sizes. For dual-panel displays, the LPP bit field should be programmed to describe either
the upper or the lower panel, and not be doubled.
ALI Active modes: LPP and LCDREV must be considered together. Program LPP to an odd
9:0
LPP
number of lines for AD-TFT and HR-TFT panels. AD-TFT and HR-TFT displays utilize the
LCDREV signal as an AC bias signal (it does not alter LCDDCLK). The LCDREV signal os-
cillates, driven HIGH during one frame and driven LOW during the next frame. To avoid long-
term LCD damage, the AC bias applied to any line of an LCD panel should average to a net
0 VDC. When correctly programmed, the LCDREV signal will be HIGH for a line during one
frame and LOW for the same line during the next frame. If the LPP bit field specifies an even
number of Lines Per Panel, this oscillation will be mismatched to the display's lines and the
lines will not receive a net 0 VDC bias. See ALITIMING1:REVDEL for additional information.
Version 1.0
4-23
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