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LH79524/LH79525 User's Guide
4.5.6.2 Control Register (ALICTRL)
ALICTRL is the Control Register. It enables and controls output signals.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:10
9
MODOVRD
8
7:5
4
3
2
1
0
Table 4-45. ALICTRL Register
31
30
29
28
27
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
///
0
0
0
0
RO
RO
RO
RO
RO
NAME
Reserved Reading returns 0. Write the reset value.
///
MOD Signal Override Enable Puts the value of MODVAL directly onto the MOD signal.
0 = LCDMOD pin goes HIGH after the SPS periods specified by the MODDEL field of
the TIMING1 Register.
1 = LCDMOD pin equals the state of MODVAL bit in this register.
MODVAL
Mod Signal Value Specifies the value to force onto the MOD signal.
///
Reserved Reading returns 0. Write the reset value.
LCDVEEEN Output Enable Specifies the general-purpose output enable to
LCDVEEEN (only in Bypass Mode).
EN0
1 = LCDVEEEN signal enabled
0 = LCDVEEEN signal disabled
Display Control Signal Output Controls the output of the Display Control signal,
LCDDSPLEN (only in Bypass Mode).
DISP
1 = LCDDSPLEN signal enabled
0 = LCDDSPLEN signal disabled
///
Reserved Reading returns 0. Write the reset value.
CLS Enable
STN or TFT (Bypass) modes: Reserved Reading returns 0. Values written cannot be read.
CLSEN
ALI mode: Enables or disables the generation of the LCDCLS (Gate Driver Clock) signal.
1 = LCDCLS signal enabled
0 = LCDCLS signal disabled
SPS Enable
STN or TFT (Bypass) modes: Reserved Reading returns 0. Values written cannot be read.
SPSEN
ALI mode: Enables or disables the generation of the LCDSPS (Row Reset) signal.
1 = LCDSPS signal is enabled
0 = LCDSPS signal is disabled
Color Liquid Crystal Display Controller
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
10
9
8
7
0
0
0
0
0
RO
RW
RW
RO
0xFFFE4000 + 0x004
Table 4-46. ALICTRL Fields
DESCRIPTION
Version 1.0
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
///
///
0
0
0
0
0
RO
RO
RW
RW
RO
17
16
0
0
RO
RO
1
0
0
0
RW
RW
4-39
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