Table 17-36. Outcsr1 Register; Table 17-37. Outcsr1 Fields; Control Status Register 1 For Out Ep1 And Ep2 (Outscsr1) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)

OUTCSR1 provides control and status bits for transfers through the currently-selected
OUT endpoint
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7
6
5
.

Table 17-36. OUTCSR1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 17-37. OUTCSR1 Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Clear Data Toggle Sequence Bit The Serial Interface Engine (SIE)
tracks the Data PID sequence toggle received for USB transactions
with multiple data packets. An error condition that requires the USB
transaction to be re-synchronized, this bit should be programmed to 1
to reset the data toggle so that the SIE expects a DATA0 packet iden-
CL_DATATOG
tifier on the next transfer. Software writes a 1 to this bit to clear the data
toggle bit. The USB block programs this bit to 0 when a read is received
from the USB Host.
1 = The data toggle sequence bit is reset to DATA0
0 = No effect
Stall Handshake Sent The USB block sets this bit to 1 when an OUT
token is ended with a STALL handshake from the USB Host. The USB
block issues a stall handshake if the Host sends more than MAXP data
SENT_STALL
for the OUT token. Software clears this bit by writing a 0.
1 = OUT token ended with a STALL handshake
0 = No STALL handshake received
Send Stall Handshake Software programs a 1 to this bit to issue a
STALL handshake to the USB Host.
SEND_STALL
1 = Issue STALL handshake to USB Host
0 = End STALL condition
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RW
0xFFFF5000 + 0x050
(with the INDEX register set to 1 or 2)
FUNCTION
Version 1.0
Universal Serial Bus Device
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RO RW
17 16
0 0
RO RO
1 0
0 0
RO RW
17-27