Table 6-5. Emac Register Summary; Memory Map - Sharp LH79524 User Manual

Ethernet MAC Controller
6.3 Register Reference
This section provides the EMAC register memory mapping and bit fields.

6.3.1 Memory Map

The base address for the EMAC is 0xFFFC7000.
Table 6-5 Summarizes the EMAC registers. There are three types of registers in the EMAC:
control, configuration, and status registers; statistics registers; and matching registers.
Address offsets in the table are from the base address. All registers are little endian format.
6-18

Table 6-5. EMAC Register Summary

ADDRESS
NAME
OFFSET
CONTROL, CONFIGURATION, AND STATUS REGISTERS
0x00 NETCTL
0x04 NETCONFIG
0x08 NETSTATUS
0x0C ///
0x10 ///
0x14 TXSTATUS
0x18 RXBQP
0x1C TXBQP
0x20 RXSTATUS
0x24 INSTATUS
0x28 ENABLE
0x2C DISABLE
0x30 MASK
0x34 PHYMAINT
0x38 PAUSETIME
0xBC TXPAUSEQUAN
STATISTICS REGISTERS
0x3C PAUSEFRRX
0x40 FRMTXOK
0x44 SINGLECOL
0x48 MULTFRM
0x4C FRMRXOK
0x50 FRCHK
0x54 ALIGNERR
0x58 DEFTXFRM
0x5C LATECOL
0x60 EXCOL
0x64 TXUNDER
Version 1.0
LH79524/LH79525 User's Guide
DESCRIPTION
Network Control Register
Network Configuration Register
Network Status Register
Reserved
Reserved
Transmit Status Register
Receive Buffer Queue Pointer
Transmit Buffer Queue Pointer
Receive Status Register
Interrupt Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
PHY Maintenance Register
Pause Time Register
Transmit pause quantum
Pause Frames Received
Frames Transmitted OK
Single Collision Frames
Multiple Collision Frames
Frames Received OK
Frame Check Sequence Errors
Alignment Errors
Deferred Transmission Frames
Late collisions
Excessive collisions
Transmit underrun errors