Table 4-49. Alitiming2 Register; Table 4-50. Alitiming2 Fields; Timing Delay Register 2 (Alitiming2) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.5.6.4 Timing Delay Register 2 (ALITIMING2)

The ALITIMING2 Register is used for various delay values for output signals. All delays
are specified in number of LCD clock (LCDDCLK) periods.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:9
8:0

Table 4-49. ALITIMING2 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
SPLDEL
0 0 0 0 0
RW RW RW RW RW

Table 4-50. ALITIMING2 Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
LCDSPL Delay Controls the delay in LCDDCLK periods of the LCDSPL sig-
nal during vertical front and back porches. This field must be programmed to
SPLDEL
a value greater than the sum of (TIMING0:HSW + TIMING0:HBP).
SPLDEL = (LCDDCLK periods) – 1
LCDSPL and LCDCLS Delay 2 Controls the delay in LCDDCLK periods
from the first rising edge of the LCDSPL signal to the trailing edge of the
PS2CLS2
LCDCLS and LCDPS signals. The value of this field must be greater than 0.
PS2CLS2 = (LCDDCLK periods) – 1
Color Liquid Crystal Display Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RW RW RW RW
0xFFFE4000 + 0x00C
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PS2CLS2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW
4-41