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LH79524/LH79525 User's Guide
16.1.1 Transmitting Data
When the UART is programmed to transmit and enabled, writing data to the transmit FIFO:
• Causes the UART to start transmitting a data frame with the parameters indicated in the
UARTLCR_H Register. Data continues to be transmitted until the transmit FIFO is
empty, as indicated by the Transmit FIFO Empty Flag (UARTFR:TXFE).
• Causes the UARTFR:BUSY bit to be asserted. This bit remains HIGH until the transmit
FIFO is empty and the last character, including the Stop bits, has been sent.
16.1.2 Receive Data Frame
A UART receive data frame structure consists of:
• A LOW Start bit that indicates the beginning of the frame.
• Five to eight data bits.
• An optional parity error/address received bit, which can be used with available hardware
for parity-error checking or can be used as an address received bit.
• One or two Stop bits, which indicate the end of the frame. The number of Stop bits is
programmable using the UARTCR_H:STP2 bit.
The UART receiver is in the Idle state (i.e., the input is 1) from the time a Stop bit is sent
until the time the next Start bit is received. When the receiver receives an entire frame, the
UART transfers the received data and the frame status to the receive FIFO. This buffer can
have a depth of either 32 12-bit words (FIFO Mode) or one 12-bit word (Character Mode),
as set with the UARTLCR_H:FEN bit.
The Start bit works with the UART bit clock to synchronize the receiver with the source driv-
ing the receiver. When the source drives the receiver input from the Idle state to 0, the
receiver waits 7/16ths of a bit period, then samples the input three times:
• Once at 7/16ths of the bit period
• Once at 8/16ths of the bit period
• Once at 9/16ths of the bit period.
If the input is 0 for at least two of the three samples, the UART recognizes a Start bit. After
recognizing the Start bit, the receiver repeats the following sequence until all data bits, any
parity bit, and all Stop bits are detected:
1.
Wait 14/16ths of a bit period, then sample the input.
2.
Wait 1/16th of a bit period, then sample the input.
3.
Wait 1/16th of a bit period, then sample the input.
4.
Choose the majority value of the three samples as the input value for that bit period.
After recognizing the final Stop bit, the UART stores the received data frames and associ-
ated status bits in the receiver FIFO.
Version 1.0
UARTs
16-3
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