Sharp LH79524 User Manual page 167

Ethernet MAC Controller
To receive frames, the buffer descriptors must be initialized by writing an appropriate
address to bits [31:2] in the first word of each list entry. Bit zero must be written with 0. Bit
one is the wrap bit and indicates the last entry in the list.
The start location of the Receive Buffer Descriptor List must be written to the
register
(NETCTL:
frame data to the receive FIFO, the receive buffer manager reads the first receive buffer
location pointed to by RXBQP.
If the Address Checking Block indicates that the frame should be copied to memory, the
receive data DMA operation starts writing data into the receive buffer. If an error occurs,
the buffer is recovered.
If the current buffer pointer has its Wrap bit set, or it is the 1,024th descriptor, the next
receive buffer location is read from the beginning of the Receive Buffer Descriptor List. Oth-
erwise, the next receive buffer location is read from the next consecutive word in memory.
The RXBQP register increments with each successful read, which indexes the 2,048 word
locations of a maximum length Receive Buffer Descriptor List. Reading the RXBQP regis-
ter returns the pointer value, which is the list entry currently being accessed. The value
written to the RXBQP register may be any word-aligned address, provided that there are
at least 2,048 word locations available between the pointer and the top of memory.
The AMBA 2.0 specification requires that bursts not cross 1KB boundaries. As receive
buffer manager Write functions are two-word bursts, the RXBQP register should be pro-
grammed with the three least-significant bits as 0.
As each receive buffer is used, the receive buffer manager programs the Used bit of the
first descriptor word to 1 to indicate that buffer has been used. If a receive error is detected,
the receive buffer currently being written will be recovered. Previous buffers will not be
recovered. Software should search through the Used bits in the buffer descriptors to deter-
mine how many frames have been received and not rely on the value returned by the
RXBQP register, which changes continuously as more buffers are used.
If the statistics registers indicate that CRC errors, excessive length frames, or length field
mismatched frames have been encountered, a frame fragment may have been stored in
a sequence of frame buffers. Software can detect this by looking for the Start Of Frame bit
set in a buffer following a buffer with no End Of Frame bit set. However, in a properly work-
ing Ethernet system, there should be no excessive length frames or frames greater than
128 bytes with CRC/FCS errors. Collision fragments will be less than 128 bytes long.
Therefore, finding a frame fragment in a receive buffer is rare.
If the Used bit is 1 when the receive buffer manager reads the location of the receive buffer,
the buffer has been already used and cannot be used again until software has processed
the frame and cleared the Used bit. In this case, the DMA Block will set the buffer not avail-
able bit in the Receive Status register (RXSTATUS) and trigger an interrupt. If the Used bit
is 1 when the receive buffer manager reads the location of the receive buffer, and a frame
is being received, that frame will be discarded and the Receive Resource Error statistics
register (RXRERR) will be incremented.
6-6
before programming the Receive Enable bit in the network control register
to enable receive. As soon as the receive block starts writing received
RXEN)
Version 1.0
LH79524/LH79525 User's Guide
RXBQP