Table 10-13. Icr Register; Table 10-14. Icr Register Definitions; Interrupt Clear Register (Icr) - Sharp LH79524 User Manual

2
I S Converter

10.2.2.6 Interrupt Clear Register (ICR)

This register is write only. Writing 1 causes the corresponding interrupt to be cleared.
Writing 0 has no effect. The value written cannot be read back.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6
5
4
3:0
10-20
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO

Table 10-14. ICR Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
SSPPEC SSP Protocol Error interrupt clear Clears the SSP Protocol Error Interrupt.
External Codec Protocol Error interrupt clear Clears the External Codec
ECPEC
Protocol Error Interrupt.
Transmit Underrun Error interrupt clear Clears the Transmit Underrun Er-
TXUEC
ror Interrupt.
/// Reserved (see SSP ICR register)

Table 10-13. ICR Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC8000 + 0x014
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
WO WO WO RO RO
17 16
0 0
RO RO
1 0
///
0 0
RO RO