Figure 1-5. Reset Circuit For Tap Controller Including A Push Button; Hardware Requirements At Reset - Sharp LH79524 User Manual

Overview
nRESETIN
PUSHBUTTON
nTRST

1.4.2 Hardware Requirements at Reset

A number of pins contain on-chip pull up or pull down resistors that provide a logic state
following reset. Other pins require external pull up or pull down resistors because their
state is read by the core prior to power becoming stable. Thus the state of these pins can-
not be guaranteed using the internal resistors.
1.4.2.1 Floating Inputs
Many applications require extremely low standby and operating current consumption,
especially in battery operated devices. For minimum current, unused inputs must never be
left floating (unconnected). Each input must be pulled up or pulled down with a 33 kΩ resis-
tor (or smaller). In addition to terminating input pins, this also allows selecting the reset
state of input pins using pull up (logical 1 at reset) or pull down (logical 0 at reset) resistors.
1.4.2.2 Test Pins
The two test pins, TEST1 and TEST2, require being tied HIGH for the SoC to boot into Nor-
mal Operation Mode. Without tying these pins HIGH, the chip may boot into PLL Bypass
Mode. To enter Embedded ICE Mode, TEST1 is pulled LOW and TEST2 pulled HIGH;
nBLE0 has a sufficient internal pull up.
1-10
RESET
V+
POWER ON RESET
V+

Figure 1-5. Reset Circuit for TAP Controller Including a Push Button

V+
V+
Version 1.0
LH79524/LH79525 User's Guide
SYSTEM RESET TO
OTHER PERIPHERALS
nRESETIN
LH79524/LH79525
nTRST
LH79525-118