Timing Formulas - Sharp LH79524 User Manual

Analog-to-Digital Converter/Brownout Detector

2.1.7 Timing Formulas

The throughput-conversion time consists of one cycle of Get Data state added to 16 cycles
of measurement. Starting from the Idle state, the time for a complete measurement
sequence, in clock cycles, is calculated as:
1CIS + MS × (TCT + STC) + 1CEOS
where:
• 1CIS is one cycle in Idle state
• MS is the number of measurements in the sequence
• TCT is the throughput conversion time of 17 cycles
• STC is the number of settling time cycles per measurement
• 1CEOS is one cycle in the End of Sequence state.
This equals:
• Two cycles, plus
• The number of measurements in sequence times, plus
• The throughput conversion time (17 cycles), plus
• The number of settling time cycles per measurement.
2.1.8 Interrupts
The ADC has five interrupts:
• Brownout Interrupt (BROWNOUTINTR)
• Pen Interrupt (PENIRQ)
• End of Sequence Interrupt
• FIFO Watermark Interrupt
• FIFO Overrun Interrupt
All five interrupts make up the combined interrupt TSCIRQ, and presented to the VIC.
Each of the five individual maskable interrupts, except Brownout, is enabled or disabled by
changing the mask bits in the IM Register (see Section 2.2.2.4). Software can read the
interrupt status bits through the IS Register, even if corresponding mask bits are set (see
Section 2.2.2.8). Clearing the mask bits does not clear the interrupt status.
2.1.8.1 Brownout Interrupt
The Brownout Interrupt (BROWNOUTINTR) is asserted when the supply voltage dips
below the trip-point voltage. This interrupt status is latched in the IS Register. It remains
HIGH until the BOIC bit of the Interrupt Clear (IC) register is asserted. The instantaneous
raw status of the BROWNOUTINTR is stored in the GS Register (see Section 2.2.2.7). The
Brownout Interrupt has its own dedicated output to the VIC.
NOTE: The latency between clearing the latched Brownout Interrupt and the time when it can be set again is
2-8
one A2DCLK cycle. Polled systems should use the unlatched Brown-Out Raw Interrupt Status bit
(bit [9]) in the GS register instead of the latched interrupt status in the IS register.
Version 1.0
LH79524/LH79525 User's Guide