Table 4-22. Lpbase Register; Table 4-23. Lpbase Register Fields; Lower Panel Frame Buffer Base Address Register (Lpbase) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE)

The LPBASE Register is one of two Color LCD DMA Base Address Registers (the other is
UPBASE, described in Section 4.5.3.4). Together with UPBASE, this Read/Write register
programs the base address of the frame buffer.
LPBASE is used for the lower panel of dual-panel STN displays. UPBASE must be initial-
ized (and LPBASE for dual panels) before enabling the CLCDC. Optionally, the value can
be changed mid-frame to allow double-buffered video displays to be created. These reg-
isters are copied to the corresponding current registers at each LCD vertical synchroniza-
tion. This event causes the BUI bit and an optional interrupt to be generated. The BUI bit
indicates that it is safe to update both the UPBASE and LPBASE Registers. The interrupt
can be used to reprogram the base address when generating double-buffered video.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:2 LCDLPBASE
1:0

Table 4-22. LPBASE Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 4-23. LPBASE Register Fields

NAME
LCD Lower Panel Base Address This is the start address of the
lower panel frame data in memory and is word-aligned.
/// Reserved Reading returns 0. Write the reset value.
Color Liquid Crystal Display Controller
26 25 24 23
LCDLPBASE
0 0 0 0
RW RW RW RW
10 9 8 7
LCDLPBASE
0 0 0 0
RW RW RW RW
0xFFFF4000 + 0x14
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RW RW
1 0
///
0 0
RO RO
4-27