Table 7-41. Dynactiveab Register; Table 7-42. Dynactiveab Fields; Dynamic Memory Active Bank A To Active Bank B Time Register (Dynactiveab) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.5.2.16 Dynamic Memory Active Bank A to Active Bank B
Time Register (DYNACTIVEAB)
The Dynamic Memory Active Bank A to Active Bank B Time Register programs the active
bank A to active bank B latency, tRRD. This value is normally found in SDRAM data sheets
as tRRD.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR

Table 7-41. DYNACTIVEAB Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-42. DYNACTIVEAB Fields

BITS NAME
31:4 /// Reserved Reading returns 0. Write the reset value.
Active Bank A to Active Bank B Latency
3:0 tRRD
Latency = (tRRD + 1) External Memory Clock periods
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x054
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
tRRD
1 1
RW RW
7-45