Table 13-24. Pclkctrl1 Register; Table 13-25. Pclkctrl1 Fields; Peripheral Clock Control Register 1 (Pclkctrl1) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.10 Peripheral Clock Control Register 1 (PCLKCTRL1)

This register controls the USB, ADC, LCD, and SSP peripheral clocks. Programming a bit
to 1 disables the corresponding peripheral's clock. The SSP Clock, USB Clock, and the
LCD Data Clock are more fully described in Table 13-1. The ADC Clock is described in
Section 2.1.3 of this User's Guide.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:4
3
2
1
0
13-20

Table 13-24. PCLKCTRL1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-25. PCLKCTRL1 Fields

/// Reserved Reading returns 0. Write the reset value.
USB Clock Enables and disables the internal 48 MHz clock to the USB Device
peripheral.
USB
1 = Stops the USB Clock
0 = Enables the USB Clock
ADC Clock Enables and disables the internal ADC clock generator.
ADC
1 = Stops the ADC Clock
0 = Enables the ADC Clock
SSP Clock (SSPCLK) Enables and disables the clock presented to the
SSPCLK pin.
SSP
1 = Stops the SSP Clock
0 = Enables the SSP Clock.
LCD Data Clock (LCDDCLK) Enables and disables the clock presented to the
Color LCD Contoller hardware and the LCDDCLK pin.
LCD
1 = Stops the LCD Data Clock
0 = Enables the LCD Data Clock
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x28
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
USB ADC
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
SSP LCD
1 1
RW RW