Figure 10-8. I 2 S Slave Mode Transmission Timing Diagram; Reception - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
EXPECTED I2STXD
EXPECTED I2STXD

10.1.4 Reception

10.1.4.1 Master Mode Reception
During Master Mode reception, the I
and frame output (PB2/SSPFRM/I2SWS). In response to signals from the I
external CODEC sends data on SSPRX_I2SRXD_IN.
PB2/SSPFRM/I2SWS is formed by toggling PB2/SSPFRM/I2SWS each time a pulse is
received by the I
the level is delayed by a clock. In this case, the data cannot be received from the external
CODEC and transmitted to the SSP in time, as depicted by Figure 10-9. For this reason,
the data received from the external CODEC in slave mode is delayed by the I
before being transmitted to the SSP on SSPTXD. This results in a one-frame lag in the
reception of data in master mode, regardless of the value of WSDEL. Until the delay pipe
is filled, the SSP will receive a logic low on SSPRXD, causing the first two entries in the
SSP Receive FIFO to be filled with 0x000.
I2SCLKIN
I2SFSSIN
(WSDEL = 0)
MSB1
(WSDEL = 1)
SSPFSSIN
(WSDEL = 0)
SSPTXD
(WSDEL = 0)
I2STXD
(WSDEL = 0)
SSPFSSIN
(WSDEL = 1)
SSPTXD
(WSDEL = 1)
I2STXD
(WSDEL = 1)
2
Figure 10-8. I S Slave Mode Transmission Timing Diagram
2
S converter from the SSP on SSPFSSOUT. If WSDEL is set to 1, then
Version 1.0
MSB1 14 1 LSB1 MSB2
14 13 LSB1 MSB2 14
MSB1 2 1 LSB1
MSB1 14 1 LSB1 MSB2
2
S converter supplies the clock (PB3/SSPCLK/I2SCLK)
2
I S Converter
14 1 LSB2 MSB3 14
13 LSB2 MSB3 14 13
MSB2 2 1 LSB2 MSB3
MSB1 14
14 1 LSB2 MSB3 13
MSB1 14 13
2
S converter, the
2
S converter
LH79525-98
10-7